74ACQ374SCX

74ACQ374SCX Datasheet


74ACQ374, 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs

Part Datasheet
74ACQ374SCX 74ACQ374SCX 74ACQ374SCX (pdf)
Related Parts Information
74ACQ374SJX 74ACQ374SJX 74ACQ374SJX
74ACQ374SJ 74ACQ374SJ 74ACQ374SJ
74ACTQ374SJ 74ACTQ374SJ 74ACTQ374SJ
74ACTQ374QSC 74ACTQ374QSC 74ACTQ374QSC
74ACTQ374QSCX 74ACTQ374QSCX 74ACTQ374QSCX
74ACTQ374SJX 74ACTQ374SJX 74ACTQ374SJX
74ACQ374SC 74ACQ374SC 74ACQ374SC
74ACQ374PC 74ACQ374PC 74ACQ374PC
74ACTQ374SC 74ACTQ374SC 74ACTQ374SC
74ACTQ374SCX 74ACTQ374SCX 74ACTQ374SCX
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74ACQ374, 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs

April 2007
74ACQ374, 74ACTQ374 tm

Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs
• ICC and IOZ reduced by 50%
• Guaranteed simultaneous switching noise level and
dynamic threshold performance
• Guaranteed pin-to-pin skew AC performance
• Improved latch-up immunity
• Buffered positive edge-triggered clock
• 3-STATE outputs drive bus lines or buffer memory
address registers
• Outputs source/sink 24mA
• Faster prop delays than the standard AC/ACT374

The ACQ/ACTQ374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable OE are common to all flip-flops.

The ACQ/ACTQ374 utilizes FACT Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.
Ordering Information

Package Order Number

Package Description
74ACQ374SC
74ACQ374SJ 74ACTQ374SC
74ACTQ374SJ 74ACTQ374QSC

M20B

M20D M20B

M20D MQA20
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

Connection Diagram

Pin Description

Pin Names CP OE

Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs

FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.
74ACQ374, 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs

Logic Symbol

IEEE/IEC

Logic Diagram

Functional Description

The ACQ/ACTQ374 consists of eight edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.

Truth Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
= LOW-to-HIGH Transition

Outputs On H L Z

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
1989 Fairchild Semiconductor Corporation
74ACQ374, 74ACTQ374 Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Parameter

VCC IIK

VI IOK

VO IO ICC or IGND TSTG

Supply Voltage DC Input Diode Current

VI = VI = VCC + 0.5V DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature DC Latch-Up Source or Sink Current

Junction Temperature

Rating to +7.0V
+20mA to VCC + 0.5V
+20mA to VCC + 0.5V ±50mA ±50mA to +150°C ±300mA 140°C

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol VCC

VI VO TA /

Parameter Supply Voltage

ACQ ACTQ Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, ACQ Devices VIN from 30% to 70% of VCC, VCC 3.0V, 4.5V, 5.5V Minimum Input Edge Rate, ACTQ Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V

Rating
2.0V to 6.0V 4.5V to 5.5V
0V to VCC 0V to VCC to +85°C 125mV/ns
More datasheets: 861A509 | 74ACQ374SJX | 74ACQ374SJ | 74ACTQ374SJ | 74ACTQ374QSC | 74ACTQ374QSCX | 74ACTQ374SJX | 74ACQ374SC | 74ACQ374PC | 74ACTQ374SC


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Datasheet ID: 74ACQ374SCX 513212