74ACTQ273SJ

74ACTQ273SJ Datasheet

74ACTQ273 Quiet Series Octal D-Type Flip-Flop

Part	Datasheet
74ACTQ273SJ	74ACTQ273SJ (pdf)

Related Parts	Information
74ACTQ273SJX	74ACTQ273SJX
74ACTQ273PC	74ACTQ273PC
74ACTQ273SC	74ACTQ273SC
74ACTQ273SCX	74ACTQ273SCX
74ACTQ273MTCX	74ACTQ273MTCX

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74ACTQ273 Quiet Series Octal D-Type Flip-Flop 74ACTQ273 Quiet Series Octal D-Type Flip-Flop The ACTQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset MR input load and reset clear all flip-flops simultaneously. The register is fully edge-triggered. The state of each Dtype input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The ACTQ utilizes Fairchild Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features output control and undershoot corrector in addition to a split ground bus for superior performance. s ICC reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s Buffered common clock and asynchronous master reset s Outputs source/sink 24 mA s 4 kV minimum ESD immunity Ordering Code: Order Number Package Number Package Description 74ACTQ273SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACTQ273SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACTQ273MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACTQ273PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Data Inputs Master Reset Clock Pulse Input Data Outputs FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 2001 Fairchild Semiconductor Corporation DS010585 74ACTQ273 Logic Symbols IEEE/IEC Mode Select-Function Table Operating Mode MR Reset Clear Load “1” Load “0” H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Transition Logic Diagram Inputs CP X Outputs Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACTQ273 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-up Source or Sink Current Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C ±300 mA 140°C Recommended Operating Conditions Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate VIN from 0.8V to 2.0V VCC 4.5V, 5.5V

PDF Datasheet Preview

74ACTQ273 Quiet Series Octal D-Type Flip-Flop
74ACTQ273 Quiet Series Octal D-Type Flip-Flop

The ACTQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset MR input load and reset clear all flip-flops simultaneously.

The register is fully edge-triggered. The state of each Dtype input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.

All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.

The ACTQ utilizes Fairchild Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features
output control and undershoot corrector in addition to a split ground bus for superior performance.
s ICC reduced by 50% s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s Buffered common clock and asynchronous master reset s Outputs source/sink 24 mA s 4 kV minimum ESD immunity
Ordering Code:

Order Number Package Number

Package Description
74ACTQ273SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACTQ273SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACTQ273MTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACTQ273PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

Data Inputs Master Reset

Clock Pulse Input

Data Outputs

FACT Quiet and are trademarks of Fairchild Semiconductor Corporation.
2001 Fairchild Semiconductor Corporation DS010585
74ACTQ273

Logic Symbols

IEEE/IEC

Mode Select-Function Table

Operating Mode MR

Reset Clear

Load “1”

Load “0”

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Transition

Logic Diagram

Inputs CP X

Outputs

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACTQ273

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-up Source or

Sink Current

Junction Temperature TJ PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±50 mA −65°C to +150°C
±300 mA
140°C

Recommended Operating Conditions

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate

VIN from 0.8V to 2.0V VCC 4.5V, 5.5V

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Datasheet ID: 74ACTQ273SJ 513209