74ACTQ16646MTD
74ACTQ16646MTD Datasheet
74ACTQ16646 16-Bit Transceiver/Register with 3-STATE Outputs
| Part | Datasheet |
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74ACTQ16646MTD |
74ACTQ16646MTD (pdf) |
| Related Parts | Information |
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74ACTQ16646MTDX |
74ACTQ16646MTDX |
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74ACTQ16646SSC |
74ACTQ16646SSC |
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74ACTQ16646SSCX |
74ACTQ16646SSCX |
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| 74ACTQ16646 16-Bit Transceiver/Register with 3-STATE Outputs 74ACTQ16646 16-Bit Transceiver/Register with 3-STATE Outputs The ACTQ16646 contains sixteen non-inverting bidirectional registered bus transceivers providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The DIR inputs determine the direction of data flow through the device. The CPAB and CPBA inputs load data into the registers on the LOW-to-HIGH transition. The ACTQ16646 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector for superior performance. s Utilizes Fairchild FACT Quiet Series technology s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin output skew s Independent registers for A and B buses s Multiplexed real-time and stored data transfers s Separate control logic for each byte s 16-bit version of the ACTQ646 s Outputs source/sink 24 mA s Additional specs for Multiple Output Switching s Output loading specs for both 50 pF and 250 pF loads Ordering Code: Order Number Package Number Package Description 74ACTQ16646SSC MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74ACTQ16646MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Assignment for SSOP and TSSOP FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS010937.prf 74ACTQ16646 Function Table Inputs Data I/O Note 1 Output Operation Mode DIR1 CPAB1 CPBA1 SAB1 SBA1 H or L H or L X Isolation Input Clock An Data into A Register Clock Bn Data Into B Register An to Time Transparent Mode Input Output Clock An Data to A Register A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn Bn to Time Transparent Mode L Output Input Clock Bn Data into B Register B Register to An Stored Mode Clock Bn into B Register and Output to An H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition. Note 1 The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O A and B 8-15 and #2 control pins. Real Time Transfer A-Bus to B-Bus Storage from Bus to Register Real Time Transfer B-Bus to A-Bus Transfer from Register to Bus 74ACTQ16646 Logic Diagram 74ACTQ16646 Absolute Maximum Ratings Note 2 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source/Sink Current IO DC VCC or Ground Current per Output Pin Storage Temperature −0.5V to +7.0V −20 mA +20 mA −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA |
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