CY7C146-25JC
CY7C146-25JC Datasheet
CY7C132/CY7C136 CY7C142/CY7C146
| Part | Datasheet |
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CY7C146-25JC |
CY7C146-25JC (pdf) |
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| CY7C132/CY7C136 CY7C142/CY7C146 2K x 8 Dual-Port Static RAM • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 2K x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access 15 ns • Low operating power ICC = 110 mA max. • Fully asynchronous operation • Automatic power-down • Master CY7C132/CY7C136 easily expands data bus width to 16 or more bits using slave CY7C142/CY7C146 • BUSY output flag on CY7C132/CY7C136 BUSY input on CY7C142/CY7C146 • INT flag for port-to-port communication 52-pin PLCC/PQFP versions • Available in 48-pin DIP CY7C132/142 , 52-pin PLCC and 52-pin TQFP CY7C136/146 • Pin-compatible and functionally equivalent to IDT7132/IDT7142 Functional Description The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132/ CY7C136 can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CY7C142/CY7C146 SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins chip enable CE , write enable R/W , and output enable OE . BUSY flags are provided on each port. In addition, an interrupt flag INT is provided on each port of the 52-pin PLCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data has been placed in a unique location 7FF for the left port and 7FE for the right port . An automatic power-down feature is controlled independently on each port by the chip enable CE pins. The CY7C132/CY7C142 are available in 48-pin DIP. The CY7C136/CY7C146 are available in 52-pin PLCC and PQFP. Logic Block Diagram R/WL CEL I/O7L I/O0L BUSYL[1] A 10L I/O CONTROL I/O CONTROL ADDRESS DECODER MEMORY ARRAY ADDRESS DECODER INTL[2] CEL OEL R/WL ARBITRATION LOGIC 7C132/7C136 ONLY AND INTERRUPTLOGIC 7C136/7C146 ONLY CER OER R/WR CY7C132/CY7C136 Master BUSY is open drain output and requires pull-up resistor. CY7C142/CY7C146 Slave BUSY is input. Open drain outputs pull-up resistor required. R/WR CER OER I/O7R I/O0R BUSYR A 10R A 0R INTR Ordering Information Speed ns Ordering Code 30 CY7C132-30PC CY7C132-30PI 35 CY7C132-35PC CY7C132-35PI CY7C132-35DMB 45 CY7C132-45PC CY7C132-45PI CY7C132-45DMB 55 CY7C132-55PC CY7C132-55PI CY7C132-55DMB 15 CY7C136-15JC CY7C136-15NC 25 CY7C136-25JC CY7C136-25NC 30 CY7C136-30JC CY7C136-30NC CY7C136-30JI 35 CY7C136-35JC CY7C136-35NC CY7C136-35JI CY7C136-35LMB 45 CY7C136-45JC CY7C136-45NC CY7C136-45JI CY7C136-45LMB 55 CY7C136-55JC CY7C136-55NC CY7C136-55JI CY7C136-55NI CY7C136-55LMB 30 CY7C142-30PC CY7C142-30PI 35 CY7C142-35PC CY7C142-35PI CY7C142-35DMB 45 CY7C142-45PC CY7C142-45PI CY7C142-45DMB 55 CY7C142-55PC Ordering Information continued Speed ns Ordering Code 15 CY7C146-15JC CY7C146-15NC 25 CY7C146-25JC CY7C146-25NC 30 CY7C146-30JC CY7C146-30NC CY7C146-30JI 35 CY7C146-35JC CY7C146-35NC CY7C146-35JI CY7C146-35LMB 45 CY7C146-45JC CY7C146-45NC CY7C146-45JI CY7C146-45LMB 55 CY7C146-55JC CY7C146-55NC CY7C146-55JI CY7C146-55LMB Package Name J69 N52 J69 N52 J69 N52 J69 N52 J69 L69 J69 N52 J69 L69 J69 N52 J69 L69 Package Type 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier Operating Range Commercial Commercial Commercial Industrial Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military MILITARY SPECIFICATIONS Group A Subgroup Characteristics Parameter VOH VOL VIH VIL Max. IIX IOZ ICC ISB1 ISB2 ISB3 ISB4 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Switching Characteristics Parameter Read Cycle tRC tAA tACE tDOE Write Cycle tWC tSCE Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Switching Characteristics continued Parameter tAW tHA tSA tPWE tSD tHD Busy/Interrupt Timing tBLA tBHA tBLC tBHC tPS tWINS tEINS tINS tOINR tEINR tINR BUSY TIMING tWB[24] tWH tBDD Note CY7C142/CY7C146 only. Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Page 13 of 17 Package Diagrams CY7C132/CY7C136 CY7C142/CY7C146 48-Lead 600-Mil Sidebraze DIP D26 MIL-STD-1835 D-14 Config. C |
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