74ACTQ16240SSCX

74ACTQ16240SSCX Datasheet

74ACTQ16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs

Part	Datasheet
74ACTQ16240SSCX	74ACTQ16240SSCX (pdf)

Related Parts	Information
74ACTQ16240MTDX	74ACTQ16240MTDX
74ACTQ16240MTD	74ACTQ16240MTD
74ACTQ16240SSC	74ACTQ16240SSC

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74ACTQ16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs 74ACTQ16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs The ACTQ16240 contains sixteen inverting buffers with 3STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The ACTQ16240 utilizes Fairchild’s Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features GTO output control for superior performance. s Utilizes Fairchild’s FACT Quiet Series technology s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin output skew s Separate control logic for each byte s 16-bit version of the ACTQ240 s Outputs source/sink 24 mA s Additional specs for multiple output switching s Output loading specs for both 50 pF and 250 pF loads Ordering Code: Order Number Package Number Package Description 74ACTQ16240SSC MS48A 48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide 74ACTQ16240MTD MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Assignment for SSOP and TSSOP Pin Descriptions Pin Names OEn Description Output Enable Inputs Active Low Inputs Outputs FACT , FACT Quiet Series , Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS010924.prf 74ACTQ16240 Truth Tables Inputs Inputs Inputs Inputs H = High Voltage Level L = Low Voltage Level X = Immaterial Z = High Impedance Outputs Outputs Outputs Outputs Functional Description The ACTQ16240 contains sixteen inverting buffers with 3STATE standard outputs. The device is nibble 4 bits controlled with each nibble functioning identically, but independently of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable OEn input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. Logic Diagram 74ACTQ16240 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source/Sink Current IO DC VCC or Ground Current per Output Pin Junction Temperature Storage Temperature −0.5V to +7.0V −20 mA +20 mA −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA +140°C −65°C to +150°C Recommended Operating Conditions Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns VIN from 0.8V to 2.0V VCC 4.5V, 5.5V Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics

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74ACTQ16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
74ACTQ16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs

The ACTQ16240 contains sixteen inverting buffers with 3STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.

The ACTQ16240 utilizes Fairchild’s Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features GTO output control for superior performance.
s Utilizes Fairchild’s FACT Quiet Series technology s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin output skew s Separate control logic for each byte s 16-bit version of the ACTQ240 s Outputs source/sink 24 mA s Additional specs for multiple output switching s Output loading specs for both 50 pF and 250 pF loads
Ordering Code:

Order Number Package Number

Package Description
74ACTQ16240SSC

MS48A
48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide
74ACTQ16240MTD

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

Pin Assignment for SSOP and TSSOP

Pin Descriptions

Pin Names OEn

Description Output Enable Inputs Active Low Inputs Outputs

FACT , FACT Quiet Series , Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS010924.prf
74ACTQ16240

Truth Tables

Inputs

Inputs

Inputs

Inputs

H = High Voltage Level L = Low Voltage Level X = Immaterial Z = High Impedance

Outputs

Outputs

Outputs

Outputs

Functional Description

The ACTQ16240 contains sixteen inverting buffers with 3STATE standard outputs. The device is nibble 4 bits controlled with each nibble functioning identically, but independently of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable OEn input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.

Logic Diagram
74ACTQ16240

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source/Sink Current IO DC VCC or Ground Current per Output Pin

Junction Temperature

Storage Temperature
−0.5V to +7.0V
−20 mA +20 mA
−20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA
± 50 mA +140°C −65°C to +150°C

Recommended Operating Conditions

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate
4.5V to 5.5V
0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns

VIN from 0.8V to 2.0V

VCC 4.5V, 5.5V

Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.

DC Electrical Characteristics

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Datasheet ID: 74ACTQ16240SSCX 513197