74ACT841SC

74ACT841SC Datasheet

74ACT841 10-Bit Transparent Latch with 3-STATE Outputs

Part	Datasheet
74ACT841SC	74ACT841SC (pdf)

Related Parts	Information
74ACT841MTC	74ACT841MTC
74ACT841SPC	74ACT841SPC
74ACT841MTCX	74ACT841MTCX
74ACT841SCX	74ACT841SCX

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74ACT841 10-Bit Transparent Latch with 3-STATE Outputs 74ACT841 10-Bit Transparent Latch with 3-STATE Outputs The ACT841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The ACT841 is a 10-bit transparent latch, a 10-bit version of the ACT373. s ACT841 has TTL-compatible inputs s Outputs source/sink 24 mA s Non-inverting 3-STATE outputs Ordering Code: Order Number Package Number Package Description 74ACT841SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACT841MTC MTC24 24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT841SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. SPC not available in Tape and Reel. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names OE LE Description Data Inputs 3-STATE Outputs Output Enable Latch Enable is a trademark of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS010156 74ACT841 Functional Description The ACT841 consists of ten D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state. Function Table Inputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Logic Diagram Internal Q X L H NC L H NC Output O Z L H NC Function High Z High Z High Z Latched Transparent Latched Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACT841 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C 140°C Recommended Operating Conditions Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate VIN from 0.8V to 2.0V VCC 4.5V, 5.5V 4.5V to 5.5V

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74ACT841 10-Bit Transparent Latch with 3-STATE Outputs
74ACT841 10-Bit Transparent Latch with 3-STATE Outputs

The ACT841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The ACT841 is a 10-bit transparent latch, a 10-bit version of the ACT373.
s ACT841 has TTL-compatible inputs s Outputs source/sink 24 mA s Non-inverting 3-STATE outputs
Ordering Code:

Order Number Package Number

Package Description
74ACT841SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACT841MTC

MTC24
24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT841SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. SPC not available in Tape and Reel.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names OE LE

Description Data Inputs 3-STATE Outputs Output Enable Latch Enable
is a trademark of Fairchild Semiconductor Corporation.
2000 Fairchild Semiconductor Corporation DS010156
74ACT841

Functional Description

The ACT841 consists of ten D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition.

On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state.

Function Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change

Logic Diagram

Internal

Q X L H NC L H NC

Output

O Z L H NC

Function

High Z High Z High Z Latched Transparent Latched

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACT841

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ

PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±50 mA −65°C to +150°C
140°C

Recommended Operating Conditions

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate

VIN from 0.8V to 2.0V VCC 4.5V, 5.5V
4.5V to 5.5V

More datasheets: XFAS01 | XFBS01 | 1096 | FIELDBUS GATEWAY | M4212 BK002 | M4212 BK005 | M4212 BK001 | 3259 | 74ACT841MTC | 74ACT841SPC

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Datasheet ID: 74ACT841SC 513184