74ACT825MTCX

74ACT825MTCX Datasheet

74ACT825 8-Bit D-Type Flip-Flop

Part	Datasheet
74ACT825MTCX	74ACT825MTCX (pdf)

Related Parts	Information
74ACT825SCX	74ACT825SCX
74ACT825SCX_SF87271A	74ACT825SCX_SF87271A
74ACT825SPC	74ACT825SPC
74ACT825SC	74ACT825SC

PDF Datasheet Preview
74ACT825 8-Bit D-Type Flip-Flop 74ACT825 8-Bit D-Type Flip-Flop The ACT825 is an 8-bit buffered register. They have Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included are multiple enables that allow multiuse control of the interface. The ACT825 has noninverting outputs. s Outputs source/sink 24 mA s Inputs and outputs are on opposite sides s TTL compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT825SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACT825MTC MTC24 24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT825SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names OE1, OE2, OE3 EN CLR CP Description Data Inputs Data Outputs Output Enables Clock Enable Clear Clock Input is a trademark of Fairchild Semiconductor. 2000 Fairchild Semiconductor Corporation DS009895 74ACT825 Functional Description The ACT825 consists of eight D-type edge-triggered flipflops. These devices have 3-STATE outputs for bus systems, organized in a broadside pinning. In addition to the clock and output enable pins, the buffered clock CP and buffered Output Enable OE are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE1, OE2 and OE3 LOW, the contents of the flip-flops are available at the outputs. When one of OE1, OE2 or OE3 is HIGH, the outputs go to the high impedance state. Function Table Operation of the OE input does not affect the state of the flip-flops. The ACT825 has Clear CLR and Clock Enable EN pins. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. Inputs CLR X H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Internal Q L H L NC L H L H Output O Z L Z NC Z L H Function High-Z High-Z Clear Hold Load Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACT825 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC +0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC +0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current Per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP −0.5V to 7.0V −20 mA +20 mA −0.5V to VCC +0.5V −20 mA +20 mA +0.5V ± 50 mA ± 50 mA −65°C to +150°C 140°C Recommended Operating Conditions Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate VIN from 0.8V to 2.0V VCC 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns

PDF Datasheet Preview

74ACT825 8-Bit D-Type Flip-Flop
74ACT825 8-Bit D-Type Flip-Flop

The ACT825 is an 8-bit buffered register. They have Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included are multiple enables that allow multiuse control of the interface. The ACT825 has noninverting outputs.
s Outputs source/sink 24 mA s Inputs and outputs are on opposite sides s TTL compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74ACT825SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACT825MTC

MTC24
24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT825SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names OE1, OE2, OE3 EN CLR CP

Description Data Inputs Data Outputs Output Enables Clock Enable Clear Clock Input
is a trademark of Fairchild Semiconductor.
2000 Fairchild Semiconductor Corporation DS009895
74ACT825

Functional Description

The ACT825 consists of eight D-type edge-triggered flipflops. These devices have 3-STATE outputs for bus systems, organized in a broadside pinning. In addition to the clock and output enable pins, the buffered clock CP and buffered Output Enable OE are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE1, OE2 and OE3 LOW, the contents of the flip-flops are available at the outputs. When one of OE1, OE2 or OE3 is HIGH, the outputs go to the high impedance state.

Function Table

Operation of the OE input does not affect the state of the flip-flops. The ACT825 has Clear CLR and Clock Enable EN pins. These pins are ideal for parity bus interfacing in high performance systems.

When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions.

Inputs

CLR X

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= High Impedance = LOW-to-HIGH Transition NC = No Change

Logic Diagram

Internal Q L H L NC L H L H

Output O Z L Z NC Z L H

Function

High-Z High-Z Clear Hold Load

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACT825

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC +0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC +0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current Per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP
−0.5V to 7.0V
−20 mA +20 mA −0.5V to VCC +0.5V
−20 mA +20 mA
+0.5V
± 50 mA
± 50 mA −65°C to +150°C
140°C

Recommended Operating Conditions

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate

VIN from 0.8V to 2.0V VCC 4.5V, 5.5V
4.5V to 5.5V
0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns

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Datasheet ID: 74ACT825MTCX 513183