74ACT823SPC
74ACT823SPC Datasheet
74ACT823 9-Bit D-Type Flip-Flop
| Part | Datasheet |
|---|---|
74ACT823SPC |
74ACT823SPC (pdf) |
| Related Parts | Information |
|---|---|
74ACT823MTCX |
74ACT823MTCX |
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74ACT823SCX |
74ACT823SCX |
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74ACT823SC |
74ACT823SC |
| PDF Datasheet Preview |
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| 74ACT823 9-Bit D-Type Flip-Flop 74ACT823 9-Bit D-Type Flip-Flop The ACT823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. The ACT823 offers noninverting outputs. s Outputs source/sink 24 mA s 3-STATE outputs for bus interfacing s Inputs and outputs are on opposite sides s TTL compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT823SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACT823MTC MTC24 24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT823SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. SPC not available in Tape and Reel. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names OE CLR CP EN Description Data Inputs Data Outputs Output Enable Clear Clock Input Clock Enable is a trademark of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS009894 74ACT823 Functional Description The ACT823 consists of nine D-type edge-triggered flipflops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The buffered clock CP and buffered Output Enable OE are common to all flip-flops. The flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. In addition to the Clock and Out- Function Table put Enable pins, there are Clear CLR and Clock Enable EN pins. These devices are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. Inputs OE CLR EN CP D H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Internal Q L H L NC L H L H Output O Z L Z NC Z L H Function High Z High Z Clear Hold Load Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACT823 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP −0.5V to 7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C 140°C Recommended Operating Conditions |
| More datasheets: 98044060352 | 98044050833 | 98044050858 | 98044060345 | STAND L | 601 | B58620S3300B360 | 74ACT823MTCX | 74ACT823SCX | 74ACT823SC |
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