74ACT715-RSC

74ACT715-RSC Datasheet


74ACT715•74ACT715-R Programmable Video Sync Generator

Part Datasheet
74ACT715-RSC 74ACT715-RSC 74ACT715-RSC (pdf)
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74ACT715•74ACT715-R Programmable Video Sync Generator
74ACT715•74ACT715-R Programmable Video Sync Generator

The ACT715 and ACT715-R are 20-pin TTL-input compatible devices capable of generating Horizontal, Vertical and Composite Sync and Blank signals for televisions and monitors. All pulse widths are completely definable by the user. The devices are capable of generating signals for both interlaced and noninterlaced modes of operation. Equalization and serration pulses can be introduced into the Composite Sync signal when needed.

Four additional signals can also be made available when Composite Sync or Blank are used. These signals can be used to generate horizontal or vertical gating pulses, cursor position or vertical Interrupt signal.

These devices make no assumptions concerning the system architecture. Line rate and field/frame rate are all a function of the values programmed into the data registers, the status register, and the input clock frequency.

The ACT715 is mask programmed to default to a Clock Disable state. Bit 10 of the Status Register, Register 0, defaults to a logic This facilitates re programming before operation.

The ACT715-R is the same as the ACT715 in all respects except that the ACT715-R is mask programmed to default
to a Clock Enabled state. Bit 10 of the Status Register defaults to a logic Although completely re programmable, the ACT715-R version is better suited for applications using the default MHz RS-170 register values. This feature allows power-up directly into operation, following a single CLEAR pulse.
s Maximum Input Clock Frequency > 130 MHz s Interlaced and non-interlaced formats available s Separate or composite horizontal and vertical Sync and

Blank signals available s Complete control of pulse width via register
programming s All inputs are TTL compatible s 8 mA drive on all outputs s Default RS170/NTSC values mask programmed into
registers s ACT715-R is mask programmed to default to a Clock

Enable state for easier start-up into MHz RS170 timing
Ordering Code:

Order Number Package Number

Package Description
74ACT715SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACT715PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACT715-RSC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACT715-RPC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignment for DIP and SOIC

FACT is a trademark of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS010137.prf
74ACT715•74ACT715-R

Logic Block Diagram

Pin Description

There are a Total of 13 inputs and 5 outputs on the ACT715.

Data Inputs The Data Input pins connect to the Address Register and the Data Input Register.

ADDR/DATA The ADDR/DATA signal is latched into the device on the falling edge of the LOAD signal. The signal determines if an address 0 or data 1 is present on the data bus.

L/HBYTE The L/HBYTE signal is latched into the device on the falling edge of the LOAD signal. The signal determines if data will be read into the 8 LSB’s 0 or the 4 MSB’s 1 of the Data Registers. A 1 on this pin when an ADDR/DATA is a 0 enables Auto-Load Mode.

LOAD The LOAD control pin loads data into the Address or Data Registers on the rising edge. ADDR/DATA and L/ HBYTE data is loaded into the device on the falling edge of the LOAD. The LOAD pin has been implemented as a Schmitt trigger input for better noise immunity.

CLOCK System CLOCK input from which all timing is derived. The clock pin has been implemented as a Schmitt trigger for better noise immunity. The CLOCK and the LOAD signal are asynchronous and independent. Output state changes occur on the falling edge of CLOCK.

CLR The CLEAR pin is an asynchronous input that initializes the device when it is HIGH. Initialization consists of setting all registers to their mask programmed values, and
initializing all counters, comparators and registers. The CLEAR pin has been implemented as a Schmitt trigger for better noise immunity. A CLEAR pulse should be asserted by the user immediately after power-up to ensure proper initialization of the if the user plans to re program the device.

Note A CLEAR pulse will disable the CLOCK on the ACT715 and will enable the CLOCK on the ACT715-R.

ODD/EVEN Output that identifies if display is in odd HIGH or even LOW field of interlace when device is in interlaced mode of operation. In noninterlaced mode of operation this output is always HIGH. Data can be serially scanned out on this pin during Scan Mode.

VCSYNC Outputs Vertical or Composite Sync signal based on value of the Status Register. Equalization and Serration pulses will if enabled be output on the VCSYNC signal in composite mode only.

VCBLANK Outputs Vertical or Composite Blanking signal based on value of the Status Register.

HBLHDR Outputs Horizontal Blanking signal, Horizontal Gating signal or Cursor Position based on value of the Status Register.

HSYNVDR Outputs Horizontal Sync signal, Vertical Gating signal or Vertical Interrupt signal based on value of Status Register.
74ACT715•74ACT715-R

Register Description

All of the data registers are 12 bits wide. Width’s of all pulses are defined by specifying the start count and end count of all pulses. Horizontal pulses are specified withrespect-to the number of clock pulses per line and vertical pulses are specified with-respect-to the number of lines per frame.

REGISTER

Disable System Clock 0 Enable System Clock 1 Default values for B10 are “0” in the ACT715 and “1” in the ACT715-R. Disable Counter Test Mode 0 Enable Counter Test Mode 1 This bit is not intended for the user but is for internal testing only.

The Status Register controls the mode of operation, the signals that are output and the polarity of these outputs. The default value for the Status Register is 0 000 Hex for the ACT715 and is “1024” 400 Hex for the ACT715-R.

Bits

HORIZONTAL INTERVAL REGISTERS

The Horizontal Interval Registers determine the number of clock cycles per line and the characteristics of the Horizontal Sync and Blank pulses.

Horizontal Front Porch

B2 B1 B0 VCBLANK VCSYNC HBLHDR 0 CBLANK CSYNC HGATE DEFAULT 0 1 VBLANK CSYNC HBLANK

HSYNVDR VGATE

VGATE

Horizontal Sync Pulse End Time Horizontal Blanking Width Horizontal Interval Width # of Clocks per Line
0 1 0 CBLANK VSYNC HGATE HSYNC VERTICAL INTERVAL REGISTERS
011 100 101 110 111

VBLANK CBLANK VBLANK CBLANK VBLANK

VSYNC CSYNC VSYNC

Bits
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Datasheet ID: 74ACT715-RSC 513180