74ACT563SC
74ACT563SC Datasheet
74ACT563 Octal Latch with 3-STATE Outputs
| Part | Datasheet |
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74ACT563SC |
74ACT563SC (pdf) |
| Related Parts | Information |
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74ACT563SCX |
74ACT563SCX |
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| 74ACT563 Octal Latch with 3-STATE Outputs 74ACT563 Octal Latch with 3-STATE Outputs April 2007 • ICC and IOZ reduced by 50% • Inputs and outputs on opposite sides of package allow easy interface with microprocessors • Useful as input or output port for microprocessors • Functionally identical to ACT573 but with inverted outputs • Outputs source/sink 24mA • ACT563 has TTL-compatible inputs The ACT563 is a high-speed octal latch with buffered common Latch Enable LE and buffered common Output Enable OE inputs. The ACT563 device is functionally identical to the ACT573, but with inverted outputs. Ordering Information Order Number Package Number Package Description 74ACT563SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram Logic Symbols Pin Descriptions Pin Names LE OE Description Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs FACT is a trademark of Fairchild Semiconductor Corporation. IEEE/IEC 74ACT563 Octal Latch with 3-STATE Outputs Functional Description The ACT563 contains eight D-type latches with 3-STATE complementary outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but that does not interfere with entering new data into the latches. Logic Diagram Function Table Inputs OE LE D HXX HH L HHH HLX LHL L HH LLX Internal Q X H L NC H L NC Output Function Z High-Z Z High-Z Z High-Z Z Latched H Transparent L Transparent NC Latched H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 1988 Fairchild Semiconductor Corporation 74ACT563 Octal Latch with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VCC IIK VI IOK VO IO ICC or IGND TSTG TJ Supply Voltage DC Input Diode Current VI = VI = VCC + 0.5V DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature Rating to +7.0V +20mA to VCC + 0.5V +20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C Recommended Operating Conditions |
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