74ACT16240MTDX

74ACT16240MTDX Datasheet

74ACT16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs

Part	Datasheet
74ACT16240MTDX	74ACT16240MTDX (pdf)

Related Parts	Information
74ACT16240SSCX	74ACT16240SSCX
74ACT16240SSC	74ACT16240SSC
74ACT16240MTD	74ACT16240MTD

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74ACT16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs 74ACT16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs The ACT16240 contains sixteen inverting buffers with 3STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. s Separate control logic for each byte s 16-bit version of the ACT240 s Outputs source/sink 24 mA s TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT16240SSC MS48A 48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide 74ACT16240MTD MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names Description Output Enable Inputs Active LOW Inputs Outputs FACT is a trademark of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS500293 74ACT16240 Truth Tables Inputs OE1 L Outputs Inputs OE2 L Inputs OE3 L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Outputs Inputs OE4 L Functional Description The ACT16240 contains sixteen inverting buffers with 3STATE standard outputs. The device is nibble 4 bits controlled with each nibble functioning identically, but independently of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable OEn input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. Logic Diagram Outputs Outputs 74ACT16240 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source/Sink Current IO DC VCC or Ground Current per Output Pin Junction Temperature Storage Temperature −0.5V to +7.0V −20 mA +20 mA −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA +140°C −65°C to +150°C Recommended Operating Conditions Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns VIN from 0.8V to 2.0V

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74ACT16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs
74ACT16240 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs

The ACT16240 contains sixteen inverting buffers with 3STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/ receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.
s Separate control logic for each byte s 16-bit version of the ACT240 s Outputs source/sink 24 mA s TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74ACT16240SSC

MS48A
48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide
74ACT16240MTD

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

Pin Descriptions

Pin Names

Description Output Enable Inputs Active LOW Inputs Outputs

FACT is a trademark of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS500293
74ACT16240

Truth Tables

Inputs

OE1 L

Outputs

Inputs

OE2 L

Inputs

OE3 L

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance

Outputs

Inputs

OE4 L

Functional Description

The ACT16240 contains sixteen inverting buffers with 3STATE standard outputs. The device is nibble 4 bits controlled with each nibble functioning identically, but independently of the other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable OEn input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.

Logic Diagram

Outputs

Outputs
74ACT16240

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source/Sink Current IO DC VCC or Ground Current per Output Pin

Junction Temperature

Storage Temperature
−0.5V to +7.0V
−20 mA +20 mA
−20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA
± 50 mA +140°C −65°C to +150°C

Recommended Operating Conditions

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate
4.5V to 5.5V
0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns

VIN from 0.8V to 2.0V

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Datasheet ID: 74ACT16240MTDX 513158