74ACTQ373SCX

74ACTQ373SCX Datasheet

74ACQ373<br>• 74ACTQ373 Quiet Octal Transparent Latch with 3-STATE Outputs

Part	Datasheet
74ACTQ373SCX	74ACTQ373SCX (pdf)

Related Parts	Information
74ACQ373SCX	74ACQ373SCX
74ACQ373SJX	74ACQ373SJX
74ACTQ373SJX	74ACTQ373SJX
74ACTQ373SJ	74ACTQ373SJ
74ACTQ373QSC	74ACTQ373QSC
74ACTQ373QSCX	74ACTQ373QSCX
74ACQ373PC	74ACQ373PC
74ACQ373SC	74ACQ373SC
74ACTQ373SC	74ACTQ373SC
74ACTQ373PC	74ACTQ373PC
74ACQ373SJ	74ACQ373SJ

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74ACQ373 • 74ACTQ373 Quiet Octal Transparent Latch with 3-STATE Outputs 74ACQ373 • 74ACTQ373 Quiet Octal Transparent Latch with 3-STATE Outputs The ACQ/ACTQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable LE is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the HIGH impedance state. The ACQ/ACTQ373 utilizes Fairchild Quiet technology to guarantee quiet output switching and improve dynamic threshold performance. features output control and undershoot corrector in addition to a split ground bus for superior performance. s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch up immunity s Eight latches in a single package s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s Faster prop delays than the standard AC/ACT373 Ordering Code: Order Number Package Number Package Description 74ACQ373SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 74ACQ373SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACQ373PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001m Wide 74ACTQ373SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 74ACTQ373SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACQT373QSC MQA20 20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide 74ACTQ373PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001m Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names LE OE Description Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS010237 74ACQ373 • 74ACTQ373 Logic Symbols IEEE/IEC Logic Diagram Functional Description The ACQ/ACTQ373 contains eight D-type latches with 3STATE standard outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGHto-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable OE input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Table Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACQ373 • 74ACTQ373 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latchup Source or Sink Current Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C ±300 mA 140°C Recommended Operating Conditions Supply Voltage VCC ACQ 2.0V to 6.0V ACTQ 4.5V to 5.5V Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate 0V to VCC 0V to VCC −40°C to +85°C ACQ Devices

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74ACQ373
• 74ACTQ373 Quiet Octal Transparent Latch with 3-STATE Outputs
74ACQ373
• 74ACTQ373

Quiet Octal Transparent Latch with 3-STATE Outputs

The ACQ/ACTQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable LE is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the HIGH impedance state.

The ACQ/ACTQ373 utilizes Fairchild Quiet technology to guarantee quiet output switching and improve dynamic threshold performance. features output control and undershoot corrector in addition to a split ground bus for superior performance.
s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch up immunity s Eight latches in a single package s 3-STATE outputs drive bus lines or buffer memory
address registers s Outputs source/sink 24 mA s Faster prop delays than the standard AC/ACT373
Ordering Code:

Order Number Package Number

Package Description
74ACQ373SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74ACQ373SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACQ373PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001m Wide
74ACTQ373SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74ACTQ373SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACQT373QSC

MQA20
20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide
74ACTQ373PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001m Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names LE OE

Description Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs

Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS010237
74ACQ373
• 74ACTQ373

Logic Symbols

IEEE/IEC

Logic Diagram

Functional Description

The ACQ/ACTQ373 contains eight D-type latches with 3STATE standard outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGHto-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable OE input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.

Truth Table

Inputs

Outputs

H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACQ373
• 74ACTQ373

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG DC Latchup Source
or Sink Current

Junction Temperature TJ PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±50 mA −65°C to +150°C
±300 mA
140°C

Recommended Operating Conditions

Supply Voltage VCC ACQ
2.0V to 6.0V

ACTQ
4.5V to 5.5V

Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate
0V to VCC 0V to VCC −40°C to +85°C

ACQ Devices

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Datasheet ID: 74ACTQ373SCX 513149