74ACQ240<br>• 74ACTQ240 Quiet Octal Buffer/Line Driver with 3-STATE Outputs
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74ACQ240SJX (pdf) |
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74ACQ240SC |
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74ACQ240PC |
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74ACQ240SJ |
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74ACQ240SCX |
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74ACQ240 • 74ACTQ240 Quiet Octal Buffer/Line Driver with 3-STATE Outputs 74ACQ240 • 74ACTQ240 Quiet Octal Buffer/Line Driver with 3-STATE Outputs The ACQ/ACTQ240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. The ACQ/ ACTQ utilizes Fairchild’s Quiet technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet features output control and undershoot corrector in addition to a split ground bus for superior performance. s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s Inverting 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s Faster prop delays than the standard ACT240 Ordering Code: Order Number Package Number Package Description 74ACQ240SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACQ240SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACQ240PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACTQ240SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACTQ240SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACTQ240QSC MQA20 20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide 74ACTQ240PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names OE1, OE2 3-STATE Output Enable Inputs Outputs Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS010234 74ACQ240 • 74ACTQ240 Logic Symbol IEEE/IEC Truth Tables H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Inputs Inputs Outputs Pins 12, 14, 16, 18 Outputs Pins 3, 5, 7, 9 74ACQ240 • 74ACTQ240 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-Up Source or Sink Current Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C ±300 mA 140°C Recommended Operating Conditions Supply Voltage VCC ACQ 2.0V to 6.0V ACTQ 4.5V to 5.5V Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate 0V to VCC 0V to VCC −40°C to +85°C ACQ Devices VIN from 30% to 70% of VCC 3.0V, 4.5V, 5.5V Minimum Input Edge Rate |
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