CD4044BCN

CD4044BCN Datasheet

CD4043BC<br>• CD4044BC Quad 3-STATE NOR R/S Latches<br>• Quad 3-STATE NAND R/S Latches

Part	Datasheet
CD4044BCN	CD4044BCN (pdf)

Related Parts	Information
CD4043BCN	CD4043BCN

PDF Datasheet Preview
CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches CD4043BC • CD4044BC Quad 3-STATE NOR R/S Latches • Quad 3-STATE NAND R/S Latches The CD4043BC are quad cross-couple 3-STATE CMOS NOR latches, and the CD4044BC are quad cross-couple 3STATE CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. There is a common 3-STATE ENABLE input for all four latches. A logic “1” on the ENABLE input connects the latch states to the Q outputs. A logic “0” on the ENABLE input disconnects the latch states from the Q outputs resulting in an open circuit condition on the Q output. The 3-STATE feature allows common bussing of the outputs. s Wide supply voltage range 3V to 15V s Low power 100 nW typ. s High noise immunity VDD typ. s Separate SET and RESET inputs for each latch s NOR and NAND configuration s 3-STATE output with common output enable • Multiple bus storage • Strobed register • Four bits of independent storage with output enable • General digital logic Ordering Code: Order Number Package Number Package Description CD4043BCM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4043BCN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide CD4044BCM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4044BCSJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide CD4044BCN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP, SOIC and SOP CD4043BC Pin Assignments for DIP and SOIC CD4044BC Top View 2002 Fairchild Semiconductor Corporation DS005967 Top View CD4043BC • CD4044BC Block Diagrams CD4043BC CD4044BC Truth Tables CD4043BC OC = 3-STATE NC = No change X = Don’t care = Dominated by S = 1 input = Dominated by R = 0 input CD4044BC CD4043BC • CD4044BC Absolute Maximum Ratings Note 1 Note 2 Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD Dual-In-Line Small Outline Lead Temperature TL Soldering, 10 seconds −0.5V to +18V −0.5V to VDD +0.5V −65°C to +150°C 700 mW 500 mW 260°C DC Electrical Characteristics Note 2 Parameter Conditions Quiescent VDD = 5V, VIN = VDD or VSS Device Current VDD = 10V, VIN = VDD or VSS VDD = 15V, VIN = VDD or VSS LOW Level \|IO\| 1 µA, VIL = 0V, VIH = VDD Output Voltage VDD = 5.0V VDD = 10V VDD = 15V HIGH Level \|IO\| 1 µA, VIL = 0V, VIH = VDD

PDF Datasheet Preview

CD4043BC
• CD4044BC Quad 3-STATE NOR R/S Latches
• Quad 3-STATE NAND R/S Latches

CD4043BC
• CD4044BC Quad 3-STATE NOR R/S Latches
• Quad 3-STATE NAND R/S Latches

The CD4043BC are quad cross-couple 3-STATE CMOS NOR latches, and the CD4044BC are quad cross-couple 3STATE CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. There is a common 3-STATE ENABLE input for all four latches. A logic “1” on the ENABLE input connects the latch states to the Q outputs. A logic “0” on the ENABLE input disconnects the latch states from the Q outputs resulting in an open circuit condition on the Q output. The 3-STATE feature allows common bussing of the outputs.
s Wide supply voltage range 3V to 15V s Low power 100 nW typ. s High noise immunity VDD typ. s Separate SET and RESET inputs for each latch s NOR and NAND configuration s 3-STATE output with common output enable
• Multiple bus storage
• Strobed register
• Four bits of independent storage with output enable
• General digital logic
Ordering Code:

Order Number Package Number

Package Description

CD4043BCM

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CD4043BCN

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

CD4044BCM

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CD4044BCSJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

CD4044BCN

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

Pin Assignments for DIP, SOIC and SOP CD4043BC

Pin Assignments for DIP and SOIC CD4044BC

Top View 2002 Fairchild Semiconductor Corporation DS005967

Top View

CD4043BC
• CD4044BC

Block Diagrams

CD4043BC

CD4044BC

Truth Tables

CD4043BC

OC = 3-STATE NC = No change X = Don’t care = Dominated by S = 1 input = Dominated by R = 0 input

CD4044BC

CD4043BC
• CD4044BC

Absolute Maximum Ratings Note 1

Note 2

Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD

Dual-In-Line

Small Outline

Lead Temperature TL Soldering, 10 seconds
−0.5V to +18V −0.5V to VDD +0.5V
−65°C to +150°C
700 mW 500 mW
260°C

DC Electrical Characteristics Note 2

Parameter

Conditions

Quiescent

VDD = 5V, VIN = VDD or VSS

Device Current

VDD = 10V, VIN = VDD or VSS

VDD = 15V, VIN = VDD or VSS

LOW Level
|IO| 1 µA, VIL = 0V, VIH = VDD

Output Voltage

VDD = 5.0V

VDD = 10V

VDD = 15V

HIGH Level
|IO| 1 µA, VIL = 0V, VIH = VDD

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Datasheet ID: CD4044BCN 513567