74ACTQ574PC

74ACTQ574PC Datasheet

74ACQ574<br>• 74ACTQ574 Quiet Octal D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
74ACTQ574PC	74ACTQ574PC (pdf)

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74ACQ574 • 74ACTQ574 Quiet Octal D-Type Flip-Flop with 3-STATE Outputs 74ACQ574 • 74ACTQ574 Quiet Octal D-Type Flip-Flop with 3-STATE Outputs The ACQ/ACTQ574 is a high-speed, low-power octal Dtype flip-flop with a buffered Common Clock CP and a buffered common Output Enable OE . The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH clock CP transition. ACQ/ACTQ574 utilizes FACT Quiet technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features output control and undershoot corrector in addition to a split ground bus for superior performance. The ACQ/ACTQ574 is functionally identical to the ACTQ374 but with different pin-out. s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Inputs and outputs on opposite sides of the package allowing easy interface with microprocessors s Functionally identical to the ACQ/ACTQ374 s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s Faster prop delays than the standard AC/ACT574 Ordering Code: Order Number Package Number Package Description 74ACQ574SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 74ACQ574SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACQ574PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACTQ574SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 74ACTQ574SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACTQ574PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names CP OE Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS010634 74ACQ574 • 74ACTQ574 Logic Symbols IEEE/IEC Logic Diagram Functional Description The ACQ/ACTQ574 consists of eight edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Function Table Inputs Internal Outputs OE CP D Function Z Hold Z Hold Z Load Z Load L Data Available H Data Available NC No Change in Data L H NC H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = High Impedance = LOW-to-HIGH Transition NC = No Change NC No Change in Data Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACQ574 • 74ACTQ574 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-Up Source or Sink Current Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C ±300 mA 140°C

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74ACQ574
• 74ACTQ574 Quiet Octal D-Type Flip-Flop with 3-STATE Outputs
74ACQ574
• 74ACTQ574

Quiet Octal D-Type Flip-Flop with 3-STATE Outputs

The ACQ/ACTQ574 is a high-speed, low-power octal Dtype flip-flop with a buffered Common Clock CP and a buffered common Output Enable OE . The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH clock CP transition.

ACQ/ACTQ574 utilizes FACT Quiet technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features output control and undershoot corrector in addition to a split ground bus for superior performance.

The ACQ/ACTQ574 is functionally identical to the ACTQ374 but with different pin-out.
s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Inputs and outputs on opposite sides of the package
allowing easy interface with microprocessors s Functionally identical to the ACQ/ACTQ374 s 3-STATE outputs drive bus lines or buffer memory
address registers s Outputs source/sink 24 mA s Faster prop delays than the standard AC/ACT574
Ordering Code:

Order Number Package Number

Package Description
74ACQ574SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74ACQ574SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACQ574PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACTQ574SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74ACTQ574SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACTQ574PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names CP OE

Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs

Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS010634
74ACQ574
• 74ACTQ574

Logic Symbols

IEEE/IEC

Logic Diagram

Functional Description

The ACQ/ACTQ574 consists of eight edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.

Function Table

Inputs

Internal Outputs

OE CP D

Function

Z Hold

Z Hold Z Load Z Load L Data Available H Data Available

NC No Change in Data

L H NC

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= High Impedance = LOW-to-HIGH Transition NC = No Change

NC No Change in Data

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACQ574
• 74ACTQ574

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-Up Source or

Sink Current

Junction Temperature TJ PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±50 mA −65°C to +150°C
±300 mA
140°C

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Datasheet ID: 74ACTQ574PC 513114