74ACTQ573SCX

74ACTQ573SCX Datasheet

74ACQ573<br>• 74ACTQ573 Quiet Octal Latch with 3-STATE Outputs

Part	Datasheet
74ACTQ573SCX	74ACTQ573SCX (pdf)

Related Parts	Information
74ACTQ573QSCX	74ACTQ573QSCX
74ACTQ573QSC	74ACTQ573QSC
74ACTQ573SJ	74ACTQ573SJ
74ACTQ573SC	74ACTQ573SC
74ACTQ573MTCX	74ACTQ573MTCX
74ACTQ573PC	74ACTQ573PC

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74ACQ573 • 74ACTQ573 Quiet Octal Latch with 3-STATE Outputs 74ACQ573 • 74ACTQ573 Quiet Octal Latch with 3-STATE Outputs The ACQ/ACTQ573 is a high-speed octal latch with buffered common Latch Enable LE and buffered common Output Enable OE inputs. The ACQ/ACTQ573 is functionally identical to the ACQ/ACTQ373 but with inputs and outputs on opposite sides of the package. The ACQ/ACTQ utilizes Fairchild’s Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features output control and undershoot corrector in addition to a split ground bus for superior performance. s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s Inputs and outputs on opposite sides of package allow easy interface with microprocessors s Outputs source/sink 24 mA Ordering Code: Order Number Package Number Package Description 74ACQ573SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACQ573SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACQ573MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACQ573PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACTQ573SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACTQ573SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACTQ573QSC MQA20 20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide 74ACTQ573MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACTQ573PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation 2000 Fairchild Semiconductor Corporation DS010633 74ACQ573 • 74ACTQ573 Functional Description The ACQ/ACTQ573 contains eight D-type latches with 3STATE output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was present on the D-type inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Truth Table Inputs Outputs H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACQ573 • 74ACTQ573 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latchup Source or Sink Current Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C ±300 mA 140°C Recommended Operating Conditions Supply Voltage VCC ACQ 2.0V to 6.0V ACTQ 4.5V to 5.5V Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate

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74ACQ573
• 74ACTQ573 Quiet Octal Latch with 3-STATE Outputs
74ACQ573
• 74ACTQ573 Quiet Octal Latch with 3-STATE Outputs

The ACQ/ACTQ573 is a high-speed octal latch with buffered common Latch Enable LE and buffered common Output Enable OE inputs. The ACQ/ACTQ573 is functionally identical to the ACQ/ACTQ373 but with inputs and outputs on opposite sides of the package. The ACQ/ACTQ utilizes Fairchild’s Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features output control and undershoot corrector in addition to a split ground bus for superior performance.
s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors s Outputs source/sink 24 mA
Ordering Code:

Order Number Package Number

Package Description
74ACQ573SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACQ573SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACQ573MTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACQ573PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACTQ573SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACTQ573SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACTQ573QSC

MQA20
20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide
74ACTQ573MTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACTQ573PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names

Data Inputs Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs

Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation
2000 Fairchild Semiconductor Corporation DS010633
74ACQ573
• 74ACTQ573

Functional Description

The ACQ/ACTQ573 contains eight D-type latches with 3STATE output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was present on the D-type inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

Logic Diagram

Truth Table

Inputs

Outputs

H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACQ573
• 74ACTQ573

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG DC Latchup Source
or Sink Current

Junction Temperature TJ PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±50 mA −65°C to +150°C
±300 mA
140°C

Recommended Operating Conditions

Supply Voltage VCC ACQ
2.0V to 6.0V

ACTQ
4.5V to 5.5V

Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate

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Datasheet ID: 74ACTQ573SCX 513113