CY7C1351F-100AC

CY7C1351F-100AC Datasheet

CY7C1351F

Part	Datasheet
CY7C1351F-100AC	CY7C1351F-100AC (pdf)

PDF Datasheet Preview
CY7C1351F 4-Mb 128K x 36 Flow-through SRAM with NoBL Architecture • Can support up to 133-MHz bus operations with zero wait states Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 128K x 36 common I/O architecture • 2.5V / 3.3V I/O power supply • Fast clock-to-output times ns for 133-MHz device ns for 117-MHz device ns for 100-MHz device ns for 66-MHz device • Clock Enable CEN pin to suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • JEDEC-standard 100 TQFP and 119 BGA packages Logic Block Diagram • Burst or interleaved burst order • Low standby power Functional Description[1] The CY7C1351F is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351F is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 133-MHz device . Write operations are controlled by the four Byte Write Select BW[A:D] and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. A0, A1, A MODE ADV/LD BWA BWB BWC BWD WE OE CE1 CE2 CE3 ZZ ADDRESS REGISTER A1 A0 D1 D0 ADV/LD C WRITE ADDRESS REGISTER Q1 Q0 A1' A0' BURST LOGIC WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC MEMORY WRITE ARRAY DRIVERS READ LOGIC SLEEP Control INPUT E REGISTER DQs DQPA DQPB DQPC DQPD Note For recommendations, please refer to the Cypress application note System Design Guidelines on Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Selection Guide Ordering Information Speed MHz Ordering Code Package Name Package Type Operating Range 133 CY7C1351F-133AC A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack Commercial CY7C1351F-133BGC BG119 119-Ball BGA 14 x 22 x mm CY7C1351F-133AI A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack Industrial CY7C1351F-133BGI BG119 119-Ball BGA 14 x 22 x mm 117 CY7C1351F-117AC A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack Commercial CY7C1351F-117BGC BG119 119-Ball BGA 14 x 22 x mm CY7C1351F-117AI A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack Industrial CY7C1351F-117BGI BG119 119-Ball BGA 14 x 22 x mm 100 CY7C1351F-100AC A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack Commercial CY7C1351F-100BGC BG119 119-Ball BGA 14 x 22 x mm CY7C1351F-100AI A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack Industrial CY7C1351F-100BGI BG119 119-Ball BGA 14 x 22 x mm CY7C1351F-66AC A101 Shaded areas contain advance information. Please contain your local sales representative for more information on ordering these parts. Notes For this waveform ZZ is tied low. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Order of the Burst sequence is determined by the status of the MODE 0= Linear, 1= Interleaved . Burst operations are optional. The IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrates CEN being used to create a pause. A write is not performed during this cycle. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. DQs are in high-Z when exiting ZZ sleep mode. Page 12 of 15 Package Diagrams 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101 CY7C1351F 51-85050-A Page 13 of 15 Package Diagrams continued 119-Lead PBGA 14 x 22 x mm BG119 CY7C1351F 51-85115-B Intel and Pentium are registered trademarks of Intel Corporation. ZBT is a trademark of Integrated Device Technology. NoBL and No Bus Latency are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. All product and company names mentioned in this document may be the trademarks of their respective holders. Page 14 of 15 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1351F Document History Page Document Title CY7C1351F 4-Mb 128K x 36 Flow-through SRAM with NoBL Architecture Document Number 38-05210 Orig. of ECN NO. Issue Date Change Description of Change 119833 01/07/03 HGK New Data Sheet 123846 01/18/03 AJH Added power-up requirements to AC test loads and waveforms information 200664 See ECN SWI Final Data Sheet Page 15 of 15

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CY7C1351F
4-Mb 128K x 36 Flow-through SRAM with NoBL Architecture
• Can support up to 133-MHz bus operations with zero wait states Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 128K x 36 common I/O architecture
• 2.5V / 3.3V I/O power supply
• Fast clock-to-output times
ns for 133-MHz device ns for 117-MHz device ns for 100-MHz device ns for 66-MHz device
• Clock Enable CEN pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP and 119 BGA packages

Logic Block Diagram
• Burst or interleaved burst order
• Low standby power

Functional Description[1]

The CY7C1351F is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351F is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 133-MHz device .

Write operations are controlled by the four Byte Write Select BW[A:D] and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

A0, A1, A

MODE

ADV/LD BWA BWB BWC BWD WE

OE CE1 CE2 CE3 ZZ

ADDRESS REGISTER

A1 A0

D1 D0

ADV/LD C

WRITE ADDRESS REGISTER

Q1 Q0

A1' A0'

BURST

LOGIC

WRITE REGISTRY AND DATA COHERENCY

CONTROL LOGIC

MEMORY

WRITE

ARRAY

DRIVERS

READ LOGIC

SLEEP Control

INPUT E REGISTER

DQs DQPA DQPB DQPC DQPD

Note For recommendations, please refer to the Cypress application note System Design Guidelines on

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

Selection Guide
Ordering Information

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
133 CY7C1351F-133AC

A101
100-Lead 14 x 20 x mm Thin Quad Flat Pack

Commercial

CY7C1351F-133BGC

BG119 119-Ball BGA 14 x 22 x mm

CY7C1351F-133AI

A101
100-Lead 14 x 20 x mm Thin Quad Flat Pack

Industrial

CY7C1351F-133BGI

BG119 119-Ball BGA 14 x 22 x mm
117 CY7C1351F-117AC

A101
100-Lead 14 x 20 x mm Thin Quad Flat Pack

Commercial

CY7C1351F-117BGC

BG119 119-Ball BGA 14 x 22 x mm

CY7C1351F-117AI

A101
100-Lead 14 x 20 x mm Thin Quad Flat Pack

Industrial

CY7C1351F-117BGI

BG119 119-Ball BGA 14 x 22 x mm
100 CY7C1351F-100AC

A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack

Commercial

CY7C1351F-100BGC

BG119 119-Ball BGA 14 x 22 x mm

CY7C1351F-100AI

A101
100-Lead 14 x 20 x mm Thin Quad Flat Pack

Industrial

CY7C1351F-100BGI

BG119 119-Ball BGA 14 x 22 x mm

CY7C1351F-66AC

A101
Shaded areas contain advance information. Please contain your local sales representative for more information on ordering these parts.

Notes For this waveform ZZ is tied low. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Order of the Burst sequence is determined by the status of the MODE 0= Linear, 1= Interleaved . Burst operations are optional. The IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrates CEN being used to create a pause. A write is not performed during this cycle. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. DQs are in high-Z when exiting ZZ sleep mode.

Page 12 of 15

Package Diagrams
100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101

CY7C1351F
51-85050-*A

Page 13 of 15

Package Diagrams continued
119-Lead PBGA 14 x 22 x mm BG119

CY7C1351F
51-85115-*B

Intel and Pentium are registered trademarks of Intel Corporation. ZBT is a trademark of Integrated Device Technology. NoBL and No Bus Latency are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. All product and company names mentioned in this document may be the trademarks of their respective holders.

Page 14 of 15

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1351F

Document History Page

Document Title CY7C1351F 4-Mb 128K x 36 Flow-through SRAM with NoBL Architecture Document Number 38-05210

Orig. of ECN NO. Issue Date Change

Description of Change
119833 01/07/03 HGK New Data Sheet
123846 01/18/03

AJH Added power-up requirements to AC test loads and waveforms information
200664 See ECN

SWI Final Data Sheet

Page 15 of 15

More datasheets: 6290 | 586-SG | 587-PG | 586-SLG | 586SN-SG | T3111 000 | 044 102 1414S 100 101 | T6483 001 | T6482 001 | 3294-15USOC/S530-A5

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Datasheet ID: CY7C1351F-100AC 507978