74AC74MTCX

74AC74MTCX Datasheet

74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop

Part	Datasheet
74AC74MTCX	74AC74MTCX (pdf)

Related Parts	Information
74AC74SCX	74AC74SCX
74AC74MTC	74AC74MTC
74AC74SJ	74AC74SJ
74AC74SJX	74AC74SJX
74AC74SC	74AC74SC
74AC74PC	74AC74PC

PDF Datasheet Preview
74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop January 2008 74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop • ICC reduced by 50% • Output source/sink 24mA • ACT74 has TTL-compatible inputs The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positivegoing pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: • LOW input to SD Set sets Q to HIGH level • LOW input to CD Clear sets Q to LOW level • Clear and Set are independent of clock • Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Information Order Number 74AC74SC 74AC74SJ 74AC74MTC 74AC74PC 74ACT74SC 74ACT74SJ 74ACT74MTC 74ACT74PC Package Number M14A M14D MTC14 N14A M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC J-STD-020B standard. 74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop Connection Diagram Logic Symbols Pin Descriptions Pin Names D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2 Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs IEEE/IEC Truth Table Each Half Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Q0 = Previous Q before LOW-to-HIGH Transition of Clock 1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1988 Fairchild Semiconductor Corporation 74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VCC IIK VI IOK VO IO ICC or IGND TSTG TJ Supply Voltage DC Input Diode Current VI = VI = VCC + DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature Rating to +7.0V +20mA to VCC + 0.5V +20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI VO TA / Parameter Supply Voltage AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V Rating 2.0V to 6.0V 4.5V to 5.5V

PDF Datasheet Preview

74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop

January 2008
74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop
• ICC reduced by 50%
• Output source/sink 24mA
• ACT74 has TTL-compatible inputs

The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positivegoing pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.

Asynchronous Inputs:
• LOW input to SD Set sets Q to HIGH level
• LOW input to CD Clear sets Q to LOW level
• Clear and Set are independent of clock
• Simultaneous LOW on CD and SD makes both Q and Q HIGH
Ordering Information

Order Number 74AC74SC 74AC74SJ 74AC74MTC
74AC74PC 74ACT74SC 74ACT74SJ 74ACT74MTC
74ACT74PC

Package Number

M14A M14D MTC14

N14A M14A M14D MTC14

N14A

Package Description 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC J-STD-020B standard.
74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop

Connection Diagram

Logic Symbols

Pin Descriptions

Pin Names

D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2

Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs

IEEE/IEC

Truth Table

Each Half

Inputs

Outputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= LOW-to-HIGH Clock Transition Q0 = Previous Q before LOW-to-HIGH Transition of Clock
1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
1988 Fairchild Semiconductor Corporation
74AC74, 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Parameter

VCC IIK

VI IOK

VO IO ICC or IGND TSTG TJ

Supply Voltage DC Input Diode Current

VI = VI = VCC + DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature

Rating to +7.0V
+20mA to VCC + 0.5V
+20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol VCC

VI VO TA /

Parameter Supply Voltage

AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V

Rating
2.0V to 6.0V 4.5V to 5.5V

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Datasheet ID: 74AC74MTCX 513109