AT49BV001AT-55JI

AT49BV001AT-55JI Datasheet


The AT49BV001A N T is a 2.7-volt-only in-system reprogrammable Flash Memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 54 mW over the industrial temperature range.

Part Datasheet
AT49BV001AT-55JI AT49BV001AT-55JI AT49BV001AT-55JI (pdf)
Related Parts Information
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PDF Datasheet Preview
• Single Supply for Read and Write to 3.6V
• Fast Read Access Time 55 ns
• Internal Program Control and Timer
• Sector Architecture

One 16K Bytes Boot Block with Programming Lockout Two 8K Bytes Parameter Blocks Two Main Memory Blocks 32K Bytes, 64K Bytes
• Fast Erase Cycle Time 3 Seconds
• Byte-by-Byte Programming 30 µs/Byte Typical
• Hardware Data Protection
• DATA Polling for End of Program Detection
• Low Power Dissipation 15 mA Active Current 50 µA CMOS Standby Current
• Typical 10,000 Write Cycles

The AT49BV001A N T is a 2.7-volt-only in-system reprogrammable Flash Memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 54 mW over the industrial temperature range.

Pin Configurations

Pin Name A0 - A16 CE OE WE RESET I/O0 - I/O7 NC

Function Addresses Chip Enable Output Enable Write Enable RESET Data Inputs/Outputs No Connect

PLCC Top View

VSOP Top View 8 x 14 mm or TSOP Top View 8 x 20 mm Type 1

A11 1 A9 2 A8 3

A13 4 A14 5 NC 6 WE 7 VCC 8 *RESET 9 A16 10 A15 11 A12 12

A7 13 A6 14 A5 15 A4 16
32 OE 31 A10 30 CE 29 I/O7 28 I/O6 27 I/O5 26 I/O4 25 I/O3 24 GND 23 I/O2 22 I/O1 21 I/O0 20 A0 19 A1 18 A2 17 A3
1-megabit 128K x 8 Single 2.7-volt

Battery-Voltage

Flash Memory

AT49BV001A AT49BV001AN AT49BV001AT AT49BV001ANT
4 A12 3 A15 2 A16 1 RESET* 32 VCC 31 WE 30 NC

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13
29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7

I/O1 14 I/O2 15 GND 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20

Note *This pin is a NC on the AT49BV001AN T .

Block Diagram

When the device is deselected, the CMOS standby current is less than 50 µA. For the AT49BV001AN T , pin 1 for the PLCC package and pin 9 for the TSOP package are no connect pins. To allow for simple in-system reprogrammability, the AT49BV001A N T does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV001A N T is performed by erasing a block of data and then programming on a byte by byte basis. The byte programming time is a fast 30 µs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

The device is erased by executing the erase command sequence the device internally controls the erase operations. There are two 8K byte parameter block sections, two main memory blocks, and one boot block.

The device has the capability to protect the data in the boot block this feature is enabled by a command sequence. The 16K-byte boot block section includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is protected from being reprogrammed.

In the AT49BV001AN T , once the boot block programming lockout feature is enabled, the contents of the boot block are permanent and cannot be changed. In the AT49BV001A T , once the boot block programming lockout feature is enabled, the contents of the boot block cannot be changed with input voltage levels of volts or less.

VCC GND

OE WE CE RESET

ADDRESS INPUTS

CONTROL LOGIC

Y DECODER

X DECODER

AT49BV001A N DATA INPUTS/OUTPUTS

I/O7 - I/O0

INPUT/OUTPUT BUFFERS

PROGRAM DATA LATCHES

Y-GATING

MAIN MEMORY BLOCK 2
64K BYTES

MAIN MEMORY BLOCK 1
32K BYTES
AT49BV001A Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code

AT49BV001A-55JI

AT49BV001A-55TI

AT49BV001A-55VI
AT49BV001AN Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code

AT49BV001AN-55JI

AT49BV001AN-55TI

AT49BV001AN-55VI
AT49BV001AT Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code

AT49BV001AT-55JI

AT49BV001AT-55TI

AT49BV001AT-55VI
AT49BV001ANT Ordering Information
tACC ns

ICC mA
Ordering Code

AT49BV001ANT-55JI

AT49BV001ANT-55TI

AT49BV001ANT-55VI

Package 32J 32T 32V

Package 32J 32T 32V

Package 32J 32T 32V

Package 32J 32T 32V

Package Type
32-Lead, Plastic, J-Leaded Chip Carrier Package PLCC
32-Lead, Thin Small Outline Package TSOP
32-Lead, Thin Small Outline Package VSOP 8 x 14 mm

Operation Range Industrial
-40° to 85° C

Operation Range Industrial
-40° to 85° C

Operation Range Industrial
-40° to 85° C

Operation Range Industrial
-40° to 85° C
14 AT49BV001A N T

Packaging Information
32J PLCC

AT49BV001A N T

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
32T TSOP

PIN 1
0º ~ 8º c

Pin 1 Identifier
More datasheets: AFCT-5745APZ | AFCT-5745ATPZ | AFCT-5745PZ | AT49BV001ANT-55TI | AT49BV001A-55JI | AT49BV001A-55TI | AT49BV001A-55VI | AT49BV001AN-55JI | AT49BV001AN-55VI | AT49BV001ANT-55JI


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Datasheet ID: AT49BV001AT-55JI 518652