74AC377SJX

74AC377SJX Datasheet

74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable

Part	Datasheet
74AC377SJX	74AC377SJX (pdf)

Related Parts	Information
74AC377SJ	74AC377SJ
74AC377SC	74AC377SC
74AC377PC	74AC377PC
74AC377SCX	74AC377SCX
74AC377MTCX	74AC377MTCX
74AC377MTC	74AC377MTC

PDF Datasheet Preview
74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable January 2008 74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable • ICC reduced by 50% • Ideal for addressable register applications • Clock enable for address and data synchronization applications • Eight edge-triggered D-type flip-flops • Buffered common clock • Outputs source/sink 24mA • See 273 for master reset version • See 373 for transparent latch version • See 374 for 3-STATE version • ACT377 has TTL-compatible inputs The AC/ACT377 has eight edge-triggered, D-type flipflops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable CE is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Ordering Information Order Number Package Number Package Description 74AC377SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74AC377SJ 74AC377MTC M20D MTC20 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT377SC 74ACT377SJ 74ACT377MTC 74ACT377PC M20B M20D MTC20 N20A 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC J-STD-020B standard. FACT is a trademark of Fairchild Semiconductor Corporation. 74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable Connection Diagram Logic Symbols Pin Descriptions Pin Names CE CP Description Data Inputs Clock Enable Active LOW Data Outputs Clock Pulse Input IEEE/IEC Mode Select-Function Table Operating Mode Load ‘1' Load ‘0' Hold Do Nothing Inputs CP CE Dn H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Outputs Qn H L No Change No Change 1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1988 Fairchild Semiconductor Corporation 74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VCC IIK VI IOK VO IO ICC or IGND TSTG TJ Supply Voltage DC Input Diode Current VI = VI = VCC + 0.5V DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature Rating to +7.0V +20mA to VCC + 0.5V +20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI VO TA / Parameter Supply Voltage AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V Rating

PDF Datasheet Preview

74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable

January 2008
74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable
• ICC reduced by 50%
• Ideal for addressable register applications
• Clock enable for address and data synchronization
applications
• Eight edge-triggered D-type flip-flops
• Buffered common clock
• Outputs source/sink 24mA
• See 273 for master reset version
• See 373 for transparent latch version
• See 374 for 3-STATE version
• ACT377 has TTL-compatible inputs

The AC/ACT377 has eight edge-triggered, D-type flipflops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable CE is LOW.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
Ordering Information

Order Number

Package Number

Package Description
74AC377SC

M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74AC377SJ 74AC377MTC

M20D MTC20
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT377SC 74ACT377SJ 74ACT377MTC
74ACT377PC

M20B M20D MTC20

N20A
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC J-STD-020B standard.

FACT is a trademark of Fairchild Semiconductor Corporation.
74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable

Connection Diagram Logic Symbols

Pin Descriptions

Pin Names CE CP

Description Data Inputs Clock Enable Active LOW Data Outputs Clock Pulse Input

IEEE/IEC

Mode Select-Function Table

Operating Mode Load ‘1' Load ‘0' Hold Do Nothing

Inputs

CP CE Dn

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= LOW-to-HIGH Clock Transition

Outputs Qn H L

No Change No Change
1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
1988 Fairchild Semiconductor Corporation
74AC377, 74ACT377 Octal D-Type Flip-Flop with Clock Enable

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Parameter

VCC IIK

VI IOK

VO IO ICC or IGND TSTG TJ

Supply Voltage DC Input Diode Current

VI = VI = VCC + 0.5V DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature

Rating to +7.0V
+20mA to VCC + 0.5V
+20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol VCC

VI VO TA /

Parameter Supply Voltage

AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V

Rating

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Datasheet ID: 74AC377SJX 513099