74ACT374SC

74ACT374SC Datasheet

74AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
74ACT374SC	74ACT374SC (pdf)

Related Parts	Information
74AC374SCX	74AC374SCX
74AC374SJ	74AC374SJ
74ACT374SJ	74ACT374SJ
74ACT374MSAX	74ACT374MSAX
74ACT374MSA	74ACT374MSA
74AC374SJX	74AC374SJX
74ACT374SJX	74ACT374SJX
74ACT374PC	74ACT374PC
74AC374SC	74AC374SC
74AC374PC	74AC374PC
74AC374MTC	74AC374MTC
74AC374MTCX	74AC374MTCX
74ACT374SCX	74ACT374SCX
74ACT374MTC	74ACT374MTC
74ACT374MTCX	74ACT374MTCX

PDF Datasheet Preview
74AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs January 2008 74AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs • ICC and IOZ reduced by 50% • Buffered positive edge-triggered clock • 3-STATE outputs for bus-oriented applications • Outputs source/sink 24mA • See 273 for reset version • See 377 for clock enable version • See 373 for transparent latch version • See 574 for broadside pinout version • See 564 for broadside pinout version with inverted outputs • ACT374 has TTL-compatible inputs The AC/ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable OE are common to all flip-flops. Ordering Information Order Number Package Number Package Description 74AC374SC 74AC374SJ 74AC374MTC 74AC374PC M20B M20D MTC20 N20A 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACT374SC 74ACT374SJ 74ACT374MSA M20B M20D MSA20 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide 74ACT374MTC 74ACT374PC MTC20 N20A 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC J-STD-020B standard. 74AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs Connection Diagram Logic Symbols IEEE/IEC Pin Description Pin Names CP OE Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs Functional Description The AC/ACT374 consists of eight edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Truth Table Inputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition Outputs On H L Z 1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1988 Fairchild Semiconductor Corporation 74AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VCC IIK VI IOK VO IO ICC or IGND TSTG TJ Supply Voltage DC Input Diode Current VI = −0.5V VI = VCC + DC Input Voltage DC Output Diode Current VO = −0.5V VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature Rating −0.5V to +7.0V −20mA +20mA −0.5V to VCC + 0.5V −20mA +20mA −0.5V to VCC + 0.5V ±50mA ±50mA −65°C to +150°C 140°C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI VO TA / Parameter Supply Voltage AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V Rating 2.0V to 6.0V 4.5V to 5.5V

PDF Datasheet Preview

74AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs

January 2008
74AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs
• ICC and IOZ reduced by 50%
• Buffered positive edge-triggered clock
• 3-STATE outputs for bus-oriented applications
• Outputs source/sink 24mA
• See 273 for reset version
• See 377 for clock enable version
• See 373 for transparent latch version
• See 574 for broadside pinout version
• See 564 for broadside pinout version with inverted
outputs
• ACT374 has TTL-compatible inputs

The AC/ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable OE are common to all flip-flops.
Ordering Information

Order Number

Package Number

Package Description
74AC374SC 74AC374SJ 74AC374MTC
74AC374PC

M20B M20D MTC20

N20A
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACT374SC 74ACT374SJ 74ACT374MSA

M20B M20D MSA20
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide
74ACT374MTC 74ACT374PC

MTC20 N20A
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC J-STD-020B standard.
74AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs

Connection Diagram

Logic Symbols

IEEE/IEC

Pin Description

Pin Names CP OE

Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs

Functional Description

The AC/ACT374 consists of eight edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.

Truth Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
= LOW-to-HIGH Transition

Outputs On H L Z
1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
1988 Fairchild Semiconductor Corporation
74AC374, 74ACT374 Octal D-Type Flip-Flop with 3-STATE Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Parameter

VCC IIK

VI IOK

VO IO ICC or IGND TSTG TJ

Supply Voltage DC Input Diode Current

VI = −0.5V VI = VCC + DC Input Voltage DC Output Diode Current VO = −0.5V VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature

Rating −0.5V to +7.0V
−20mA +20mA −0.5V to VCC + 0.5V
−20mA +20mA −0.5V to VCC + 0.5V ±50mA ±50mA −65°C to +150°C 140°C

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol VCC

VI VO TA /

Parameter Supply Voltage

AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V

Rating
2.0V to 6.0V 4.5V to 5.5V

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 74ACT374SC Datasheet file may be downloaded here without warranties.

Datasheet ID: 74ACT374SC 513098