CY62128BLL-70ZXET

CY62128BLL-70ZXET Datasheet

CY62128B

Part	Datasheet
CY62128BLL-70ZXET	CY62128BLL-70ZXET (pdf)

Related Parts	Information
CY62128BLL-70SXC	CY62128BLL-70SXC
CY62128BLL-70SC	CY62128BLL-70SC
CY62128BLL-70ZC	CY62128BLL-70ZC
CY62128BLL-70ZXI	CY62128BLL-70ZXI
CY62128BLL-70ZRXE	CY62128BLL-70ZRXE
CY62128BLL-70ZRXET	CY62128BLL-70ZRXET
CY62128BLL-70ZXE	CY62128BLL-70ZXE

PDF Datasheet Preview
CY62128B 128K x 8 Static RAM • Temperature Ranges Commercial 0°C to 70°C Industrial to 85°C Automotive to 125°C • 4.5V 5.5V operation • CMOS for optimum speed/power • Low active power 70 ns, LL version, Commercial, Industrial mW max. 15 mA • Low standby power 70 ns, LL version, Commercial, Industrial 110 µW max. 15 µA • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2, and OE options Functional Description[1] The CY62128B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable CE1 , an active HIGH Chip Enable CE2 , an active LOW Output Enable OE , and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking Chip Enable One CE1 and Write Enable WE inputs LOW and Chip Enable Two CE2 input HIGH. Data on the eight I/O pins I/O0 through I/O7 is then written into the location specified on the address pins A0 through A16 . Reading from the device is accomplished by taking Chip Enable One CE1 and Output Enable OE LOW while forcing Write Enable WE and Chip Enable Two CE2 HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins I/O0 through I/O7 are placed in a high-impedance state when the device is deselected CE1 HIGH or CE2 LOW , the outputs are disabled OE HIGH , or during a write operation CE1 LOW, CE2 HIGH, and WE LOW . The CY62128B is available in a standard 450-mil-wide SOIC, 32-pin TSOP type I and STSOP packages. Logic Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 CCEE12 WE ROW DECODER SENSE AMPS INPUT BUFFER 512x 256x 8 ARRAY COLUMN DECODER POWER DOWN I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 Note For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 CY62128B Product Portfolio Product CY62128BLL Industrial Industrial Automotive Pin Configurations Min. VCC Range V Typ.[2] Max. Speed ns Power Dissipation Operating, ICC mA Typ.[2] Max. Standby, ISB2 µA Typ.[2] Max. Top View SOIC NC 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 Ordering Information Mode Power-down Power-down Read Write Selected, Outputs Disabled Power Standby ISB Standby ISB Active ICC Active ICC Active ICC Speed ns Ordering Code CY62128BLL-55SI CY62128BLL-55SXI CY62128BLL-55SC CY62128BLL-55SXC CY62128BLL-55ZI CY62128BLL-55ZXI CY62128BLL-55ZAI CY62128BLL-55ZAXI CY62128BLL-55ZRI CY62128BLL-70SI CY62128BLL-70SXI CY62128BLL-70SC CY62128BLL-70SXC CY62128BLL-70SE CY62128BLL-70SXE CY62128BLL-70ZI CY62128BLL-70ZXI CY62128BLL-70ZC CY62128BLL-70ZXC CY62128BLL-70ZE CY62128BLL-70ZXE CY62128BLL-70ZAI CY62128BLL-70ZAXI CY62128BLL-70ZAE CY62128BLL-70ZAXE CY62128BLL-70ZRXE Package Name S34 Z32 ZA32 ZR32 S34 Z32 ZA32 ZR32 Operating Range Industrial Commercial Industrial Commercial Automotive Industrial Commercial Automotive Industrial Automotive Page 8 of 11 Package Diagrams 32-Lead 450 MIL Molded SOIC S34 CY62128B BSC. MIN. MAX. SEATING PLANE 51-85081-B 32-Lead Thin Small Outline Package Type I 8x20 mm Z32 JUI Changed CE to CE1 and added CE2 0.3V in Data Retention Characteristics table Removed these part numbers from Ordering Information table CY62128BLL-55ZC, CY62128BLL-55ZAC, CY62128BLL-55ZRC, CY62128BLL-70ZAC, CY62128BLL-70ZRI, CY62128BLL-70ZRC B 239134 See ECN AJU Added Thermal Resistance table Added Automotive product information *C 321335 See ECN AJU Added Pb-free package information Page 11 of 11

PDF Datasheet Preview

CY62128B
128K x 8 Static RAM
• Temperature Ranges Commercial 0°C to 70°C Industrial to 85°C Automotive to 125°C
• 4.5V 5.5V operation
• CMOS for optimum speed/power
• Low active power
70 ns, LL version, Commercial, Industrial mW max. 15 mA
• Low standby power 70 ns, LL version, Commercial, Industrial 110 µW max. 15 µA
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options

Functional Description[1]

The CY62128B is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable CE1 , an active HIGH Chip Enable CE2 , an active LOW Output Enable OE , and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected.

Writing to the device is accomplished by taking Chip Enable One CE1 and Write Enable WE inputs LOW and Chip Enable Two CE2 input HIGH. Data on the eight I/O pins I/O0 through I/O7 is then written into the location specified on the address pins A0 through A16 . Reading from the device is accomplished by taking Chip Enable One CE1 and Output Enable OE LOW while forcing Write Enable WE and Chip Enable Two CE2 HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins I/O0 through I/O7 are placed in a high-impedance state when the device is deselected CE1 HIGH or CE2 LOW , the outputs are disabled OE HIGH , or during a write operation CE1 LOW, CE2 HIGH, and WE LOW . The CY62128B is available in a standard 450-mil-wide SOIC, 32-pin TSOP type I and STSOP packages.

Logic Block Diagram

A0 A1 A2 A3 A4 A5 A6 A7 A8

CCEE12 WE

ROW DECODER SENSE AMPS

INPUT BUFFER
512x 256x 8 ARRAY

COLUMN DECODER

POWER DOWN

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16

Note For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CY62128B

Product Portfolio

Product CY62128BLL Industrial

Industrial Automotive

Pin Configurations

Min.

VCC Range V Typ.[2]

Max.

Speed ns

Power Dissipation

Operating, ICC mA

Typ.[2] Max.

Standby, ISB2 µA

Typ.[2] Max.

Top View

SOIC

NC 1 A16 2

A14 3 A12 4

A7 5 A6 6 A5 7

A4 8 A3 9
Ordering Information

Mode Power-down Power-down Read Write Selected, Outputs Disabled

Power Standby ISB Standby ISB Active ICC Active ICC Active ICC

Speed ns
Ordering Code

CY62128BLL-55SI

CY62128BLL-55SXI

CY62128BLL-55SC

CY62128BLL-55SXC

CY62128BLL-55ZI

CY62128BLL-55ZXI

CY62128BLL-55ZAI

CY62128BLL-55ZAXI

CY62128BLL-55ZRI

CY62128BLL-70SI

CY62128BLL-70SXI

CY62128BLL-70SC

CY62128BLL-70SXC

CY62128BLL-70SE

CY62128BLL-70SXE

CY62128BLL-70ZI

CY62128BLL-70ZXI

CY62128BLL-70ZC

CY62128BLL-70ZXC

CY62128BLL-70ZE

CY62128BLL-70ZXE

CY62128BLL-70ZAI

CY62128BLL-70ZAXI

CY62128BLL-70ZAE

CY62128BLL-70ZAXE

CY62128BLL-70ZRXE

Package Name S34 Z32 ZA32 ZR32 S34 Z32 ZA32 ZR32

Operating Range Industrial

Commercial

Industrial Commercial Automotive Industrial Commercial Automotive Industrial Automotive

Page 8 of 11

Package Diagrams
32-Lead 450 MIL Molded SOIC S34

CY62128B

BSC.

MIN.

MAX.

SEATING PLANE
51-85081-*B
32-Lead Thin Small Outline Package Type I 8x20 mm Z32
JUI Changed CE to CE1 and added CE2 0.3V in Data Retention Characteristics table Removed these part numbers from Ordering Information table CY62128BLL-55ZC, CY62128BLL-55ZAC, CY62128BLL-55ZRC, CY62128BLL-70ZAC, CY62128BLL-70ZRI, CY62128BLL-70ZRC
*B 239134 See ECN

AJU Added Thermal Resistance table Added Automotive product information
*C 321335 See ECN AJU Added Pb-free package information

Page 11 of 11

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Datasheet ID: CY62128BLL-70ZXET 519456