74AC163PC

74AC163PC Datasheet

74AC163<br>• 74ACT163 Synchronous Presettable Binary Counter

Part	Datasheet
74AC163PC	74AC163PC (pdf)

Related Parts	Information
74ACT163SC	74ACT163SC
74ACT163SCX	74ACT163SCX
74ACT163SJ	74ACT163SJ
74AC163SCX	74AC163SCX
74ACT163SJX	74ACT163SJX
74AC163SJ	74AC163SJ
74ACT163MTC	74ACT163MTC
74AC163SC	74AC163SC
74AC163MTCX	74AC163MTCX
74AC163MTC	74AC163MTC
74AC163SJX	74AC163SJX
74ACT163MTCX	74ACT163MTCX
74ACT163PC	74ACT163PC

PDF Datasheet Preview
74AC163 • 74ACT163 Synchronous Presettable Binary Counter 74AC163 • 74ACT163 Synchronous Presettable Binary Counter The AC/ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The AC/ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. s ICC reduced by 50% s Synchronous counting and loading s High-speed synchronous expansion s Typical count rate of 125 MHz s Outputs source/sink 24 mA s ACT163 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC163SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body 74AC163SJ M16D 16-Lead Small Outline Package, SOP , EIAJ TYPE II, 5.3mm Wide 74AC163MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74AC163PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACT163SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body 74ACT163SJ M16D 16-Lead Small Outline Package, SOP , EIAJ TYPE II, 5.3mm Wide 74ACT163MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT163PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names CEP CET CP SR PE TC Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Synchronous Reset Input Parallel Data Inputs Parallel Enable Input Flip-Flop Outputs Terminal Count Output 2000 Fairchild Semiconductor Corporation DS009932 74AC163 • 74ACT163 Logic Symbols IEEE/IEC Mode Select Table SR PE CET H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial CEP Action on the Rising Clock Edge X Reset Clear X Load Pn Qn H Count Increment X No Change Hold L No Change Hold Functional Description The AC/ACT163 counts in modulo-16 binary sequence. From state 15 HHHH it increments to state 0 LLLL . The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence synchronous reset, parallel load, count-up and hold. Four control Reset SR , Parallel Enable PE , Count Enable Parallel CEP and Count Enable Trickle the mode of operation, as shown in the Mode Select Table. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data Pn inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and SR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The AC/ACT163 uses D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count TC output is HIGH when CET is HIGH and counter is in state To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. Logic Equations Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET 74AC163 • 74ACT163 State Diagram Block Diagram FIGURE Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74AC163 • 74ACT163 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C 140°C Recommended Operating Conditions Supply Voltage VCC AC 2.0V to 6.0V

PDF Datasheet Preview

74AC163
• 74ACT163 Synchronous Presettable Binary Counter
74AC163
• 74ACT163 Synchronous Presettable Binary Counter

The AC/ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The AC/ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock.
s ICC reduced by 50% s Synchronous counting and loading s High-speed synchronous expansion s Typical count rate of 125 MHz s Outputs source/sink 24 mA s ACT163 has TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74AC163SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body
74AC163SJ

M16D
16-Lead Small Outline Package, SOP , EIAJ TYPE II, 5.3mm Wide
74AC163MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74AC163PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACT163SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body
74ACT163SJ

M16D
16-Lead Small Outline Package, SOP , EIAJ TYPE II, 5.3mm Wide
74ACT163MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT163PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names CEP CET CP SR PE TC

Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Synchronous Reset Input Parallel Data Inputs Parallel Enable Input Flip-Flop Outputs Terminal Count Output
2000 Fairchild Semiconductor Corporation DS009932
74AC163
• 74ACT163

Logic Symbols

IEEE/IEC

Mode Select Table

SR PE CET

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

CEP Action on the Rising Clock Edge X Reset Clear X Load Pn Qn H Count Increment X No Change Hold L No Change Hold

Functional Description

The AC/ACT163 counts in modulo-16 binary sequence. From state 15 HHHH it increments to state 0 LLLL . The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence synchronous reset, parallel load, count-up and hold. Four control Reset SR , Parallel Enable PE , Count Enable Parallel CEP and Count Enable Trickle the mode of operation, as shown in the Mode Select Table. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data Pn inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and SR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.

The AC/ACT163 uses D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.

The Terminal Count TC output is HIGH when CET is HIGH and counter is in state To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways.

Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters.

Logic Equations Count Enable = CEP
• CET
• PE

TC = Q0
• Q1
• Q2
• Q3
• CET
74AC163
• 74ACT163

State Diagram

Block Diagram

FIGURE

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74AC163
• 74ACT163

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ

PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±50 mA −65°C to +150°C
140°C

Recommended Operating Conditions

Supply Voltage VCC AC
2.0V to 6.0V

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 74AC163PC Datasheet file may be downloaded here without warranties.

Datasheet ID: 74AC163PC 513082