74AC161SCX

74AC161SCX Datasheet

74AC161<br>• 74ACT161 Synchronous Presettable Binary Counter

Part	Datasheet
74AC161SCX	74AC161SCX (pdf)

Related Parts	Information
74AC161MTC	74AC161MTC
74ACT161SCX	74ACT161SCX
74ACT161MTCX	74ACT161MTCX
74ACT161MTC	74ACT161MTC
74ACT161SC	74ACT161SC
74AC161PC	74AC161PC
74ACT161PC	74ACT161PC
74AC161MTCX	74AC161MTCX
74AC161SJ	74AC161SJ
74ACT161SJX	74ACT161SJX
74AC161SC	74AC161SC
74ACT161SJ	74ACT161SJ
74AC161SJX	74AC161SJX

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74AC161 • 74ACT161 Synchronous Presettable Binary Counter 74AC161 • 74ACT161 Synchronous Presettable Binary Counter The AC/ACT161 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The AC/ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. s ICC reduced by 50% s Synchronous counting and loading s High-speed synchronous expansion s Typical count rate of 125 MHz s Outputs source/sink 24 mA s ACT161 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC161SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74AC161SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74AC161MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74AC161PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACT161SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74ACT161SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACT161MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT161PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Logic Symbols IEEE/IEC Pin Descriptions Pin Names CEP CET CP MR PE TC Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Asynchronous Master Reset Input Parallel Data Inputs Parallel Enable Inputs Flip-Flop Outputs Terminal Count Output is a trademark of Fairchild Semiconductor Corporation. 2003 Fairchild Semiconductor Corporation DS009931 74AC161 • 74ACT161 Functional Description The AC/ACT161 count in modulo-16 binary sequence. From state 15 HHHH they increment to state 0 LLLL . The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs except due to Master Reset of the AC/ACT161 occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence asynchronous reset, parallel load, count-up and hold. Five control Reset, Parallel Enable PE , Count Enable Parallel CEP and Count Enable Trickle determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on the Parallel Data Pn inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The AC/ACT161 use D-type edge-triggered flip-flops and changing the PE, CEP, and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count TC output is HIGH when CET is HIGH and counter is in state To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle requires 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that lim- its the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. Logic Equations Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET Mode Select Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial X H X L Action on the Rising Clock Edge Reset Clear Load Count Increment No Change Hold No Change Hold State Diagram FIGURE Multistage Counter with Ripple Carry FIGURE Multistage Counter with Lookahead Carry 74AC161 • 74ACT161 Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74AC161 • 74ACT161 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C 140°C Recommended Operating Conditions

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74AC161
• 74ACT161 Synchronous Presettable Binary Counter
74AC161
• 74ACT161 Synchronous Presettable Binary Counter

The AC/ACT161 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The AC/ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW.
s ICC reduced by 50% s Synchronous counting and loading s High-speed synchronous expansion s Typical count rate of 125 MHz s Outputs source/sink 24 mA s ACT161 has TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74AC161SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74AC161SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74AC161MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74AC161PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACT161SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74ACT161SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACT161MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT161PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Logic Symbols

IEEE/IEC

Pin Descriptions

Pin Names CEP CET CP MR PE TC

Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Asynchronous Master Reset Input Parallel Data Inputs Parallel Enable Inputs Flip-Flop Outputs Terminal Count Output
is a trademark of Fairchild Semiconductor Corporation.
2003 Fairchild Semiconductor Corporation DS009931
74AC161
• 74ACT161

Functional Description

The AC/ACT161 count in modulo-16 binary sequence. From state 15 HHHH they increment to state 0 LLLL . The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs except due to Master Reset of the AC/ACT161 occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence asynchronous reset, parallel load, count-up and hold. Five control Reset, Parallel Enable PE , Count Enable Parallel CEP and Count Enable Trickle determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on the Parallel Data Pn inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.

The AC/ACT161 use D-type edge-triggered flip-flops and changing the PE, CEP, and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.

The Terminal Count TC output is HIGH when CET is HIGH and counter is in state To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways.

Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle requires 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that lim-
its the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. Logic Equations Count Enable = CEP
• CET
• PE

TC = Q0
• Q1
• Q2
• Q3
• CET

Mode Select Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

X H X L

Action on the Rising Clock Edge Reset Clear Load Count Increment No Change Hold No Change Hold

State Diagram

FIGURE Multistage Counter with Ripple Carry

FIGURE Multistage Counter with Lookahead Carry
74AC161
• 74ACT161

Block Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74AC161
• 74ACT161

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ

PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±50 mA −65°C to +150°C
140°C

Recommended Operating Conditions

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Datasheet ID: 74AC161SCX 513080