74AC821SCX

74AC821SCX Datasheet

74AC821<br>• 74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
74AC821SCX	74AC821SCX (pdf)

Related Parts	Information
74AC821SC	74AC821SC
74AC821SPC	74AC821SPC

PDF Datasheet Preview
74AC821 • 74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs 74AC821 • 74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs The AC/ACT821 is a 10-bit D-type flip-flop with 3-STATE outputs arranged in a broadside pinout. s 3-STATE outputs for bus interfacing s Noninverting outputs s Outputs source/sink 24 mA s TTL compatible inputs Ordering Code: Order Number Package Number Package Description 74AC821SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74AC821SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACT821SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACT821MTC MTC24 24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT821SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. SPC not available in Tape and Reel. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names OE CP Description Data Inputs Data Outputs Output Enable Input Clock Input is a trademark of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS010139 74AC821 • 74ACT821 Functional Description The AC/ACT821 consists of ten D-type edge-triggered flipflops. The buffered Clock CP and buffered Output Enable OE are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW the contents of the flip-flops are available at the outputs. When OE is HIGH the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Function Table OE H L H = HIGH Voltage Level L = LOW Voltage Level = HIGH Impedance = LOW-to-HIGH Clock Transition Logic Diagram Inputs CP Internal Outputs Function High Z High Z Load Load Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74AC821 • 74ACT821 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = − 0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP − 0.5V to + 7.0V − 20 mA + 20 mA − 0.5V to VCC + 0.5V − 20 mA + 20 mA − 0.5V to VCC + 0.5V ± 50 mA ± 50 mA − 65°C to + 150°C 140°C Recommended Operating Conditions Supply Voltage VCC AC

PDF Datasheet Preview

74AC821
• 74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs
74AC821
• 74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs

The AC/ACT821 is a 10-bit D-type flip-flop with 3-STATE outputs arranged in a broadside pinout.
s 3-STATE outputs for bus interfacing s Noninverting outputs s Outputs source/sink 24 mA s TTL compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74AC821SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74AC821SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACT821SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACT821MTC

MTC24
24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT821SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. SPC not available in Tape and Reel.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names OE CP

Description Data Inputs Data Outputs Output Enable Input Clock Input
is a trademark of Fairchild Semiconductor Corporation.
2000 Fairchild Semiconductor Corporation DS010139
74AC821
• 74ACT821

Functional Description

The AC/ACT821 consists of ten D-type edge-triggered flipflops. The buffered Clock CP and buffered Output Enable OE are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition.

With OE LOW the contents of the flip-flops are available at the outputs. When OE is HIGH the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.

Function Table

OE H L

H = HIGH Voltage Level L = LOW Voltage Level
= HIGH Impedance = LOW-to-HIGH Clock Transition

Logic Diagram

Inputs CP

Internal Outputs

Function

High Z

High Z

Load

Load

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74AC821
• 74ACT821

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = − 0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ

PDIP
− 0.5V to + 7.0V
− 20 mA + 20 mA − 0.5V to VCC + 0.5V
− 20 mA + 20 mA − 0.5V to VCC + 0.5V
± 50 mA
± 50 mA − 65°C to + 150°C
140°C

Recommended Operating Conditions

Supply Voltage VCC AC

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Datasheet ID: 74AC821SCX 513069