74ABT543CMSAX

74ABT543CMSAX Datasheet


74ABT543 Octal Registered Transceiver with 3-STATE Outputs

Part Datasheet
74ABT543CMSAX 74ABT543CMSAX 74ABT543CMSAX (pdf)
Related Parts Information
74ABT543CMTC 74ABT543CMTC 74ABT543CMTC
74ABT543CMTCX 74ABT543CMTCX 74ABT543CMTCX
74ABT543CSC 74ABT543CSC 74ABT543CSC
74ABT543CSCX 74ABT543CSCX 74ABT543CSCX
74ABT543CMSA 74ABT543CMSA 74ABT543CMSA
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74ABT543 Octal Registered Transceiver with 3-STATE Outputs
74ABT543 Octal Registered Transceiver with 3-STATE Outputs

The ABT543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow.
s Back-to-back registers for storage s Bidirectional data path s A and B outputs have current sourcing capability of 32
mA and current sinking capability of 64 mA
s Separate controls for data flow in each direction s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF
loads s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire
power up and power down cycle s Nondestructive hot insertion capability
Ordering Code:

Order Number Package Number

Package Description
74ABT543CSC 74ABT543CMSA

M24B MSA24
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 24-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide
74ABT543CMTC

MTC24
24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Assignment for SOIC, SSOP and TSSOP

Pin Names OEAB, OEBA LEAB, LEBA CEAB, CEBA

Description Output Enable Inputs Latch Enable Inputs Chip Enable Inputs Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs
1999 Fairchild Semiconductor Corporation DS011508.prf
74ABT543

Functional Description

The ABT543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable CEAB input must be low in order to enter data from the A Port or take data from the B Port as indicated in the Data I/O Control Table. With CEAB low, a low signal on LEAB input makes the A to B latches transparent a subsequent low to high transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA.

Logic Diagram

Data I/O Control Table

Inputs

CEAB LEAB OEAB

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Latch Status

Latched Transparent

Output Buffers

HIGH Z

HIGH Z Driving
74ABT543

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin
−0.5V to +7.0V

Input Voltage Note 2
−0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Any Output
in the Disable or Power-Off State
−0.5V to +5.5V
in the HIGH State Current Applied to Output
−0.5V to VCC
in LOW State Max
twice the rated IOL mA
More datasheets: 94816 | 94799 | HSMQ-C280 | 19210 | B66417G0000X608 | M3635 SL001 | M3635 SL002 | M3635 SL005 | 2006 | 17-21SURC/S530-A2/TR8


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Datasheet ID: 74ABT543CMSAX 513060