74ABT240CSCX

74ABT240CSCX Datasheet

74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs

Part	Datasheet
74ABT240CSCX	74ABT240CSCX (pdf)

Related Parts	Information
74ABT240CMTCX	74ABT240CMTCX
74ABT240CMTC	74ABT240CMTC
74ABT240CMSAX	74ABT240CMSAX
74ABT240CSJ	74ABT240CSJ
74ABT240CSJX	74ABT240CSJX
74ABT240CMSA	74ABT240CMSA
74ABT240CSC	74ABT240CSC

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74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs 74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs The ABT240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability Ordering Code: Order Number Package Number Package Description 74ABT240CSC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ABT240CSJ M20D Pb-Free 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ABT240CMSA MSA20 20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide 74ABT240CMTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Descriptions Pin Names OE1, OE2 Truth Tables Description 3-STATE Output Enable Inputs Outputs Inputs Outputs Pins 12, 14, 16, 18 Inputs H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Outputs Pins 3, 5, 7, 9 H L Z 2005 Fairchild Semiconductor Corporation DS011664 74ABT240 Absolute Maximum Ratings Note 1 Recommended Operating Storage Temperature to Conditions Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Any Output in the Disabled or mA to mA Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate 'V/'t Data Input Enable Input 50 mV/ns 20 mV/ns Power-Off State to 5.5V in the HIGH State Current Applied to Output to VCC in LOW State Max DC Latchup Source Current twice the rated IOL mA Across Comm Operating Range Over Voltage Latchup I/O mA 10V Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2 Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current IBVI Input HIGH Current Breakdown Test

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74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs
74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs

The ABT240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density.
s Output sink capability of 64 mA, source capability of 32 mA
s Guaranteed latchup protection s High impedance glitch free bus loading during entire
power up and power down cycle s Nondestructive hot insertion capability
Ordering Code:

Order Number Package Number

Package Description
74ABT240CSC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ABT240CSJ

M20D

Pb-Free 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ABT240CMSA

MSA20
20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide
74ABT240CMTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B.

Connection Diagram

Pin Descriptions

Pin Names OE1, OE2

Truth Tables

Description 3-STATE Output Enable Inputs Outputs

Inputs

Outputs Pins 12, 14, 16, 18

Inputs

H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance

Outputs

Pins 3, 5, 7, 9 H L Z
2005 Fairchild Semiconductor Corporation DS011664
74ABT240

Absolute Maximum Ratings Note 1

Recommended Operating

Storage Temperature
to Conditions

Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Any Output
in the Disabled or
mA to mA

Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate 'V/'t

Data Input Enable Input
50 mV/ns 20 mV/ns

Power-Off State
to 5.5V
in the HIGH State Current Applied to Output
to VCC
in LOW State Max DC Latchup Source Current
twice the rated IOL mA

Across Comm Operating Range Over Voltage Latchup I/O
mA 10V

Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

Note 2 Either voltage limit or current limit is sufficient to protect inputs.

DC Electrical Characteristics

VIH VIL VCD VOH

Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage

Output LOW Voltage

Input HIGH Current

IBVI

Input HIGH Current Breakdown Test

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Datasheet ID: 74ABT240CSCX 513046