74ABT16373CSSC

74ABT16373CSSC Datasheet

74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs

Part	Datasheet
74ABT16373CSSC	74ABT16373CSSC (pdf)

Related Parts	Information
74ABT16373CMTDX	74ABT16373CMTDX
74ABT16373CMTD	74ABT16373CMTD
74ABT16373CSSCX	74ABT16373CSSCX

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74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs 74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs The ABT16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the outputs are in high Z state. s Separate control logic for each byte s 16-bit version of the ABT373 s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability s Guaranteed latch-up protection Ordering Code: Order Number Package Number Package Description 74ABT16373CSSC MS48A 48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide 74ABT16373CMTD MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names OEn LEn Description Output Enable Input Active LOW Latch Enable Input Data Inputs Outputs 1999 Fairchild Semiconductor Corporation DS011666 74ABT16373 Functional Description The ABT16373 contains sixteen D-type latches with 3STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable LEn input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3STATE standard outputs are controlled by the Output Enable OEn input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagrams Truth Tables Inputs Outputs Z L H Previous Inputs Outputs Z L H Previous H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Previous = previous output prior to HIGH-to-LOW transition of LE 74ABT16373 Absolute Maximum Ratings Note 1 Recommended Operating Storage Temperature −65°C to +150°C Conditions Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Any Output −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to mA Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate Data Input Enable Input −40°C to +85°C +4.5V to +5.5V 50 mV/ns 20 mV/ns in the Disabled or Power-Off State −0.5V to +5.5V in the HIGH State Current Applied to Output −0.5V to VCC in LOW State Max twice the rated IOL mA DC Latchup Source Current OE Pin −350 mA

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74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs
74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs

The ABT16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the outputs are in high Z state.
s Separate control logic for each byte s 16-bit version of the ABT373 s High impedance glitch free bus loading during entire
power up and power down cycle s Non-destructive hot insertion capability s Guaranteed latch-up protection
Ordering Code:

Order Number Package Number

Package Description
74ABT16373CSSC

MS48A
48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide
74ABT16373CMTD

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

Pin Descriptions

Pin Names

OEn LEn

Description Output Enable Input Active LOW Latch Enable Input Data Inputs Outputs
1999 Fairchild Semiconductor Corporation DS011666
74ABT16373

Functional Description

The ABT16373 contains sixteen D-type latches with 3STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable LEn input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3STATE standard outputs are controlled by the Output Enable OEn input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.

Logic Diagrams

Truth Tables

Inputs

Outputs

Z L H Previous

Inputs

Outputs

Z L H Previous

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Previous = previous output prior to HIGH-to-LOW transition of LE
74ABT16373

Absolute Maximum Ratings Note 1

Recommended Operating

Storage Temperature
−65°C to +150°C Conditions

Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Any Output
−55°C to +125°C −55°C to +150°C
−0.5V to +7.0V −0.5V to +7.0V −30 mA to mA

Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate

Data Input Enable Input
−40°C to +85°C +4.5V to +5.5V
50 mV/ns 20 mV/ns
in the Disabled or

Power-Off State
−0.5V to +5.5V
in the HIGH State Current Applied to Output
−0.5V to VCC
in LOW State Max
twice the rated IOL mA

DC Latchup Source Current OE Pin
−350 mA

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Datasheet ID: 74ABT16373CSSC 513034