DM7473N

DM7473N Datasheet

DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

Part	Datasheet
DM7473N	DM7473N (pdf)

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DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is HIGH the J and K inputs are disabled. On the negative transition of the clock, the data from the master is transferred to the slave. The logic states of the J and K inputs must not be allowed to change while the clock is HIGH. Data transfers to the outputs on the falling edge of the clock pulse. A LOW logic level on the clear input will reset the outputs regardless of the logic states of the other inputs. Ordering Code: Order Number Package Number Package Description DM7473N N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Connection Diagram Function Table Inputs Outputs CLR CLK X Toggle H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level = Positive pulse data. the J and K inputs must be held constant while the clock is HIGH. Data is transferred to the outputs on the falling edge of the clock pulse. Q0 = The output logic level before the indicated input conditions were established. Toggle = Each output changes to the complement of its previous level on each HIGH level clock pulse. 2001 Fairchild Semiconductor Corporation DS006525 DM7473 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0°C to +70°C −65°C to +150°C Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current fCLK Clock Frequency Note 3 Pulse Width Clock HIGH Note 3 Clock LOW Clear LOW Input Setup Time Note 2 Note 3 Input Hold Time Note 2 Note 3 Free Air Operating Temperature

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DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is HIGH the J and K inputs are disabled. On the
negative transition of the clock, the data from the master is transferred to the slave. The logic states of the J and K inputs must not be allowed to change while the clock is HIGH. Data transfers to the outputs on the falling edge of the clock pulse. A LOW logic level on the clear input will reset the outputs regardless of the logic states of the other inputs.
Ordering Code:

Order Number Package Number

Package Description

DM7473N

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Connection Diagram

Function Table

Inputs

Outputs

CLR CLK
X

Toggle

H = HIGH Logic Level L = LOW Logic Level
X = Either LOW or HIGH Logic Level = Positive pulse data. the J and K inputs must be held constant while the clock is HIGH. Data is transferred to the outputs on the falling
edge of the clock pulse. Q0 = The output logic level before the indicated input conditions were
established. Toggle = Each output changes to the complement of its previous level on
each HIGH level clock pulse.
2001 Fairchild Semiconductor Corporation DS006525

DM7473

Absolute Maximum Ratings Note 1

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range
7V 5.5V 0°C to +70°C −65°C to +150°C

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

Clock Frequency Note 3

Pulse Width

Clock HIGH

Note 3

Clock LOW

Clear LOW

Input Setup Time Note 2 Note 3

Input Hold Time Note 2 Note 3

Free Air Operating Temperature

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Datasheet ID: DM7473N 513626