CYII4SC014K-EVAL

CYII4SC014K-EVAL Datasheet


CYII4SC014KAA-GTC CYII4SM014KAA-GEC

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IBIS4-14000 14-MegaPixel CMOS Image Sensor

The IBIS4-14000 is a CMOS active pixel image sensor that is comprised of 14 MegaPixels with 3048 x 4560 active pixels on an 8m pitch. The sensor has a focal plane array of 36 x 24mm2 and operates in rolling shutter mode. At 15 MHz, 3 fps are achieved at full resolution. On-chip FPN correction is available The pixel design is based on the high-fill-factor active pixel sensor technology of Cypress Semiconductor Corporation US patent No. 6,225,670 and others . The sensor is available in a monochrome version and a Bayer RGB patterned color filter array. This data sheet allows the user to develop a camera system based on the described timing and interfacing.
• Digital photography
• Document scanning
• Biometrics

Table Key Performance Parameters

Parameter Active Pixels Pixel Size Optical format Shutter Type Master Clock Frame rate Sensitivity 650 nm Full Well Charge kTC Noise Dark current Dynamic Range Supply Voltage Power Consumption Color Filter Array Packaging

Typical Value 3048 H x 4560 V 8 um x 8 um 35 mm Rolling Shutter 15 MHz 3 fps at full resolution 1256 V.m2/W.s e35 e223 e-/s dB 3.3V < 176 mW Mono and RGB 49-pins PGA

Logic Block Diagram

RESET SYR
4560 Row drivers y shift register
4560 Row drivers
y shift register
pixel array 4560 x 3048 active pixels

CLK_YL SYNC_YL

SHS SHR

CLK_X SYNC_X

Pixel 0,0 3048 column amplifiers x-shift register

CLK_YR SYNC_YR
4 parallel analog outputs
• San Jose, CA 95134-1709
• 408-943-2600
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CYII4SC014KAA-GTC CYII4SM014KAA-GEC
Ordering Information

Marketing Part Number CYII4SM014KAA-GEC CYII4SM014KAA-GECH CYII4SM014KAA-GWC CYII4SM014K-EVAL

Description Mono Standard Grade with Glass Mono High Grade with Glass Mono Standard Grade without Glass Mono Demo Kit

Package 49 pin PGA Demo Kit

Architecture and Operation

Floor Plan

The basic architecture of the sensor is shown in the Logic Block Diagram on page The Y shift registers point at a row of imager arrays. The imager arrays row is selected by the row drivers or reset by them. There are two Y shift registers, one points at the row that is read out and the other points at the row to be reset. The second pointer may lead the first pointer by a specific number of rows. In that case, the time difference between both pointers is the integration time. Alternatively, both shift registers can point at the same row for reset and readout for a faster reset sequence. When the row is read out, it is also reset. This is to do double sampling for fixed pattern noise reduction.

The pixel array of the IBIS4-14000 consists of 4536 x 3024 active pixels and 24 additional columns and rows which can be addressed see Figure The column amplifiers read out the pixel information and perform the double sampling operation. They also multiplex the signals on the readout buses which are buffered by the output amplifiers.

The shift registers can be configured for various subsampling modes. The output amplifiers can be individually powered down and some other extra functions are available. These options are configurable via a serial input port.

Figure Location of the 24 Additional Columns and Rows, Scan Direction of the Array
24 x 4536 dummy pixels

Top of camera
3024 x 24 dummy pixels
3024 x 4536 active pixels 3048 x 4560 total pixels ------------- SKY -------------4 analog outputs
pixel 0,0

Pixel Specifications

Figure Pixel and Column Structure Schematic

VDD_ ARRAY

Column PC

RESET

SELECT M2

Architecture

The pixel is a classic three transistor active pixel. The photodiode is a high-fill-factor n-well/p-substrate diode. The chip has separate power supplies for the following:
• General power supply for the analog image core VDD
• Power supply for the reset line drivers VDDR
• Separate power supply for the pixel itself VDDARRAY .

FPN and PRNU

Fixed Pattern Noise correction is done on-chip using the Double Sampling technique. The pixel is read out and this voltage value is sampled on the capacitor SHS. After read out the pixel is reset again and this value is sampled by SHR. Both sample and reset values of each pixel are subtracted in the column amplifiers to subtract FPN. Raw images taken by the sensor typically feature a residual local FPN of RMS of the saturation voltage.

The Photo Response Non Uniformity PRNU , caused by mismatch of photodiode node capacitances, is not corrected on-chip. Measurements indicate that the typical PRNU is less than1% RMS of the signal level.

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Color Filter Array CFA Figure Color Filter Arrangement on the Pixels

Output Stage

Unity gain buffers are implemented as output amplifiers. These amplifiers can be directly DC-coupled to the analog-digital converter or coupled to an external programmable gain amplifier.

The dark reference offset of the output signal is adjustable between 1.7V and 3V. The amplifier output signal is negative going with increasing light levels, with a max. amplitude of 1.2V at 4V reset voltage, in hard reset mode . The output signal range of the output amplifiers is between 0.5V and 3V.

Notes on analog video signal and output amplifier specifications:
• Video polarity the video signal is negative going with increasing light level.

The IBIS4-14000 can also be processed with a Bayer RGB color pattern. Pixel 0,0 has a green filter and is situated on a green-red row.

Figure 4 shows the response of the color filter array as a function of the wavelength. Note that this response curve includes the optical cross talk and the NIR filter of the color glass lid as well see “Cover Glass” on page 24 for response of the color glass lid .
• Signal offset the analog offset of the video signal is settable by an external DC bias pin 12 DARKREF . The settable range is between 1.7V and 3V, with 2.65V being the nominal expected set point. Hence, the output range including 1.2V video signal is between 3V and 0.5V.
• Power control the output amplifiers can be switched between an “operating” mode and a “standby” mode via the serial port of the imager see “SPI Register ” on page 12 for the configuration .
Ordering information update+package spec label. Moved figure captions to the top of the figures and moved notes to the bottom of the page per new template. Verified all cross-referencing. Moved the specifications towards the back. Corrected all variables on the Master pages.
2220967

See ECN

Eval kit section is removed. Reference to Defect Spec is added. Defect description for a RCCA added.
2765859

NVEA
09/18/09 Updated Ordering Information table

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

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Datasheet ID: CYII4SC014K-EVAL 508200