MPC97H74 Rev 4, 1/2005
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MPC97H74FA (pdf) |
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Freescale Semiconductor Technical Data V 1:14 LVCMOS PLL Clock Generator MPC97H74 The MPC97H74 is a V compatible, 1:14 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 125 MHz and output skews less than 175 ps the device meets the needs of the most demanding clock applications. V 1:14 LVCMOS PLL CLOCK GENERATOR • 1:14 PLL based low-voltage clock generator • V power supply • Internal power-on reset • Generates clock signals up to 125 MHz • Maximum output skew of 175 ps • Two LVCMOS PLL reference clock inputs • External PLL feedback supports zero-delay capability • Various feedback and output dividers see application section FA SUFFIX 52-LEAD LQFP PACKAGE CASE 848D-03 • Supports up to three individual generated output clock frequencies • Drives up to 28 clock lines • Ambient temperature range -40°C to +85°C • Pin and function compatible to the MPC974 • 52-lead Pb-free Package Available AE SUFFIX Functional Description 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE The MPC97H74 utilizes PLL technology to frequency lock its outputs onto an CASE 848D-03 input reference clock. Normal operation of the MPC97H74 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC97H74 features frequency programmability between the three output bank outputs as well as the output to input relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2, and 3:2:1 can be realized. Additionally, the device supports a separate configurable feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_SEL pin provides an extended PLL input reference frequency range. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The MPC97H74 has an internal power-on reset. The MPC97H74 is fully V compatible and requires no external loop filter components. All inputs except XTAL accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC97H74 outputs can drive one or two traces giving the devices an |
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