MPC97H73FA

MPC97H73FA Datasheet

Order Number MPC97H73/D Rev 0, 10/2003

Part	Datasheet
MPC97H73FA	MPC97H73FA (pdf)

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MOTOROLA SEMICONDUCTOR TECHNFIrCeAeLsDcAaTAle Semiconductor, Inc. Freescale Semiconductor, Inc... 3.3V 1:12 LVCMOS PLL Clock Generator MPC97H73 The MPC97H73 is a 3.3V compatible, 1:12 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications. Features • 1:12 PLL based low-voltage clock generator 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR • 3.3V power supply • Internal reset • Generates clock signals up to 240 MHz • Maximum output skew of 250 ps • Differential PECL reference clock input • Two LVCMOS PLL reference clock inputs • External PLL feedback supports zero-delay capability • Various feedback and output dividers see application section • Supports up to three individual generated output clock frequencies • Synchronous output clock stop circuitry for each individual output for power down support FA SUFFIX 52 LEAD LQFP PACKAGE CASE 848D • Drives up to 24 clock lines • Ambient temperature range 0°C to +70°C • Pin and function compatible to the MPC973 Functional Description The MPC97H73 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC97H73 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC97H73 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a factor. The MPC97H73 also supports the 180° phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals. The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be individually disabled stopped in logic low state by programming the serial CLOCK_STOP interface of the MPC97H73. The MPC97H73 has an internal reset. The MPC97H73 is fully 3.3V compatible and requires no external loop filter components. All inputs except PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 W transmission lines. For series terminated transmission lines, each of the MPC97H73 outputs can drive one or two traces giving the devices an effective fanout of The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package. Motorola, Inc. 2003 For1 More Information On This Product, Go to: Freescale Semiconductor, Inc... MPC97H73 Freescale Semiconductor, Inc. All input resistors have a value of PCLK CCLK0 CCLK1 CCLK_SEL 1 VCC 0 1

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MOTOROLA

SEMICONDUCTOR

TECHNFIrCeAeLsDcAaTAle

Semiconductor,

Inc.

Freescale Semiconductor, Inc...
3.3V 1:12 LVCMOS PLL Clock Generator

MPC97H73

The MPC97H73 is a 3.3V compatible, 1:12 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications.

Features
• 1:12 PLL based low-voltage clock generator
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
• 3.3V power supply
• Internal reset
• Generates clock signals up to 240 MHz
• Maximum output skew of 250 ps
• Differential PECL reference clock input
• Two LVCMOS PLL reference clock inputs
• External PLL feedback supports zero-delay capability
• Various feedback and output dividers see application section
• Supports up to three individual generated output clock frequencies
• Synchronous output clock stop circuitry for each individual output for power down support

FA SUFFIX 52 LEAD LQFP PACKAGE

CASE 848D
• Drives up to 24 clock lines
• Ambient temperature range 0°C to +70°C
• Pin and function compatible to the MPC973

Functional Description The MPC97H73 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC97H73 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC97H73 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and

The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a factor. The MPC97H73 also supports the 180° phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals.

The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.

The outputs can be individually disabled stopped in logic low state by programming the serial CLOCK_STOP interface of the MPC97H73. The MPC97H73 has an internal reset.

The MPC97H73 is fully 3.3V compatible and requires no external loop filter components. All inputs except PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 W transmission lines. For series terminated transmission lines, each of the MPC97H73 outputs can drive one or two traces giving the devices an effective fanout of The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.

Motorola, Inc. 2003

For1 More Information On This Product, Go to:

Freescale Semiconductor, Inc...

MPC97H73

Freescale Semiconductor, Inc.

All input resistors have a value of

PCLK

CCLK0 CCLK1 CCLK_SEL
1 VCC 0 1

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Datasheet ID: MPC97H73FA 635592