MPC9774AE

MPC9774AE Datasheet

Order Number MPC9774/D Rev 2, 05/2003

Part	Datasheet
MPC9774AE	MPC9774AE (pdf)

Related Parts	Information
MPC9774FA	MPC9774FA

PDF Datasheet Preview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V 1:14 LVCMOS PLL Clock Generator The MPC9774 is a 3.3V compatible, 1:14 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 125 MHz and output skews less than 175 ps the device meets the needs of the most demanding clock applications. Features • 1:14 PLL based low-voltage clock generator • 3.3V power supply • Internal reset • Generates clock signals up to 125 MHz • Maximum output skew of 175 ps • Two LVCMOS PLL reference clock inputs • External PLL feedback supports zero-delay capability • Various feedback and output dividers see application section • Supports up to three individual generated output clock frequencies • Drives up to 28 clock lines • Ambient temperature range 0°C to +70°C • Pin and function compatible to the MPC974 MPC9774 3.3V 1:14 LVCMOS PLL CLOCK GENERATOR FA SUFFIX 52 LEAD LQFP PACKAGE CASE 848D Functional Description The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate configurable feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_SEL pin provides an extended PLL input reference frequency range. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The MPC9774 has an internal reset. The MPC9774 is fully 3.3V compatible and requires no external loop filter components. All inputs except XTAL accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the devices an effective fanout of The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package. Motorola, Inc. 2003 MPC9774 CCLK0 CCLK1 CCLK_SEL VCC 0 1 All input resistors have a value of ÷2 0 ÷4 1 200-500 MHz FB_IN PLL_EN VCO_SEL FSEL_A FSEL_B FSEL_C FSEL_FB[1:0] ÷2, ÷4 ÷2, ÷4 ÷4, ÷6 ÷4, ÷6, ÷8, ÷12 VCC CLK_STOP VCC MR/OE POWER-ON RESET Figure MPC9774 Logic Diagram Bank A CLK STOP Bank B CLK STOP Bank C CLK STOP QA0 QA1 QA2 QA3 QA4 QB0 QB1 QB2 QB3 QB4 QC0 QC1 QC2 QC3 GND QB1 VCC QB2 GND QB3 VCC QB4 FB_IN GND QFB VCC NC QB0 VCC NC GND QC3 VCC QC2 GND QC1 VCC QC0 GND VCO_SEL 39 38 37 36 35 34 33 32 31 30 29 28 27 MPC9774 1 2 3 4 5 6 7 8 9 10 11 12 13

PDF Datasheet Preview

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA
3.3V 1:14 LVCMOS PLL Clock Generator

The MPC9774 is a 3.3V compatible, 1:14 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 125 MHz and output skews less than 175 ps the device meets the needs of the most demanding clock applications.

Features
• 1:14 PLL based low-voltage clock generator
• 3.3V power supply
• Internal reset
• Generates clock signals up to 125 MHz
• Maximum output skew of 175 ps
• Two LVCMOS PLL reference clock inputs
• External PLL feedback supports zero-delay capability
• Various feedback and output dividers see application section
• Supports up to three individual generated output clock frequencies
• Drives up to 28 clock lines
• Ambient temperature range 0°C to +70°C
• Pin and function compatible to the MPC974

MPC9774
3.3V 1:14 LVCMOS PLL CLOCK GENERATOR

FA SUFFIX 52 LEAD LQFP PACKAGE

CASE 848D

Functional Description The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range.

The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate configurable feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_SEL pin provides an extended PLL input reference frequency range.

The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.

The MPC9774 has an internal reset.

The MPC9774 is fully 3.3V compatible and requires no external loop filter components. All inputs except XTAL accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the devices an effective fanout of The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package.

Motorola, Inc. 2003

MPC9774

CCLK0 CCLK1 CCLK_SEL

VCC 0 1

All input resistors have a value of
÷2 0 ÷4 1
200-500 MHz

FB_IN

PLL_EN VCO_SEL

FSEL_A FSEL_B FSEL_C FSEL_FB[1:0]
÷2, ÷4 ÷2, ÷4 ÷4, ÷6 ÷4, ÷6, ÷8, ÷12

VCC CLK_STOP

VCC MR/OE

POWER-ON RESET Figure MPC9774 Logic Diagram

Bank A CLK STOP

Bank B CLK STOP

Bank C CLK STOP

QA0 QA1 QA2 QA3 QA4

QB0 QB1 QB2 QB3 QB4

QC0 QC1 QC2 QC3

GND QB1 VCC QB2 GND QB3 VCC QB4 FB_IN GND QFB VCC NC

QB0 VCC

NC GND QC3 VCC QC2 GND QC1 VCC QC0 GND VCO_SEL
39 38 37 36 35 34 33 32 31 30 29 28 27

MPC9774
1 2 3 4 5 6 7 8 9 10 11 12 13

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Datasheet ID: MPC9774AE 635591