MPC962308DT-1H

MPC962308DT-1H Datasheet

Order number MPC962308 Rev 3, 08/2004

Part	Datasheet
MPC962308DT-1H	MPC962308DT-1H (pdf)

Related Parts	Information
MPC962308D-1H	MPC962308D-1H
MPC962308D-1	MPC962308D-1

PDF Datasheet Preview
Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA V Zero Delay Buffer The MPC962308 is a V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. The MPC962308 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. The input-to-output skew is guaranteed to be less than 250 ps and output-to-output skew is guaranteed to be less than 200 ps. MPC962308 • 1:8 outputs LVCMOS zero-delay buffer • Zero input-output propagation delay, adjustable by the capacitive load on FBK input • Multiple Configurations, see Table Available MPC962308 Configurations • Multiple low-skew outputs • 200 ps max output-output skew • 700 ps max device-device skew • Two banks of four outputs, output tristate control by two select inputs • Supports a clock I/O frequency range of 10 MHz to 133 MHz • Low jitter, 200 ps max cycle-cycle -1, -1H, -4, -5H • ±250 ps static phase offset SPO • 16-pin SOIC package or 16-pin TSSOP package • Single V supply • Ambient temperature range to +85°C • Compatible with the CY2308 and CY23S08 • Spread spectrum compatible D SUFFIX 16-LEAD SOIC PACKAGE CASE 751B-05 DT SUFFIX 16-LEAD TSSOP PACKAGE CASE 948F-01 Functional Description The MPC962308 has two banks of four outputs each which can be controlled by the select inputs as shown in Table Select Input Decoding. Bank B can be tristated if all of the outputs are not required. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. The MPC962308 PLL enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate and there is less than 50 µA of current draw. The PLL shuts down in two additional cases explained in Table Select Input Decoding. Multiple MPC962308 devices can accept and distribute the same input clock throughout the system. In this situation, the difference between the output skews of two devices will be less than 700 ps. The MPC962308 is available in five different configurations as shown in Table Available MPC962308 Configurations. In the MPC962308-1, the reference frequency is reproduced by the PLL and provided at the outputs. A high drive version of this configuration, the MPC962308-1H, is available to provide faster rise and fall times of the device. The MPC962308-2 provides 2X and 1X the reference frequency at the output banks. In addition, the MPC962308-3 provides 4X and 2X the reference frequency at the output banks. The output banks driving the feedback will determine the different configurations of the above devices. The MPC962308-4 provides outputs 2X the reference frequency.The MPC962308-5H is a high drive version with outputs of REF/2. The MPC962308 is fully V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines on the incident edge. Depending on the configuration, the device is offered in a 16-lead SOIC or 16-lead TSSOP package. Motorola, Inc. 2004 For More Information On This Product, Go to: Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MPC962308 Block Diagram Extra Divider -3, -4 Extra Divider -5H Select Input Decoding MUX /2 Extra Divider -2, -3 FBK CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 Pin Configuration SOIC/TSSOP Top View REF 1 CLKA1 2 CLKA2 3 VDD 4 GND 5 CLKB1 6 CLKB2 7 16 FBK 15 CLKA4 14 CLKA3 13 VDD Ordering Information Available Ordering Code MPC962308D-1 MPC962308D-1R2 MPC962308D-1H MPC962308D-1HR2 MPC962308DT-1H MPC962308DT-1HR2 MPC962308D-2 MPC962308D-2R2 Ordering Information Planned Ordering Code MPC962308D-3 MPC962308D-3R2 MPC962308D-4 MPC962308D-4R2 MPC962308D-5H MPC962308D-5HR2 MPC962308DT-5H MPC962308DT-5HR2 Package Name D16 DT16 D16 Package Type 16-pin 150-mil SOIC 16-pin 150-mil SOIC Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC Tape and Reel 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC Tape and Reel Package Name D16 DT16 Package Type 16-pin 150-mil SOIC 16-pin 150-mil SOIC Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC Tape and Reel 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP Tape and Reel MOTOROLA For More Informat7ion On This Product, Go to: TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC962308 PIN'S NUMBER PIN 1 INDEX PACKAGE DIMENSIONS D SUFFIX 16 LEAD SOIC PACKAGE CASE 751B-05 ISSUE K M T A B SEATING PLANE NOTES DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.62MM. SECTION A-A Freescale Semiconductor, Inc... TIMING SOLUTIONS For More Informat8ion On This Product, Go to: MOTOROLA MPC962308 Freescale Semiconductor, Inc. PACKAGE DIMENSIONS DT SUFFIX 16 LEAD TSSOP PACKAGE CASE 948F-01 ISSUE O 2X L/2 PIN 1 IDENT. -T- SEATING PLANE K 16X REF M T U S V S SECTION N-N DETAIL E DETAIL E NOTES DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION MILLIMETER. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED PER SIDE. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED PER SIDE. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS DIM MIN MAX C --- INCHES

PDF Datasheet Preview

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

V Zero Delay Buffer

The MPC962308 is a V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. The MPC962308 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. The input-to-output skew is guaranteed to be less than 250 ps and output-to-output skew is guaranteed to be less than 200 ps.

MPC962308
• 1:8 outputs LVCMOS zero-delay buffer
• Zero input-output propagation delay, adjustable by the capacitive load on

FBK input
• Multiple Configurations, see Table Available MPC962308

Configurations
• Multiple low-skew outputs
• 200 ps max output-output skew
• 700 ps max device-device skew
• Two banks of four outputs, output tristate control by two select inputs
• Supports a clock I/O frequency range of 10 MHz to 133 MHz
• Low jitter, 200 ps max cycle-cycle -1, -1H, -4, -5H
• ±250 ps static phase offset SPO
• 16-pin SOIC package or 16-pin TSSOP package
• Single V supply
• Ambient temperature range to +85°C
• Compatible with the CY2308 and CY23S08
• Spread spectrum compatible

D SUFFIX 16-LEAD SOIC PACKAGE

CASE 751B-05

DT SUFFIX 16-LEAD TSSOP PACKAGE

CASE 948F-01

Functional Description

The MPC962308 has two banks of four outputs each which can be controlled by the select inputs as shown in Table Select Input Decoding. Bank B can be tristated if all of the outputs are not required. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. The MPC962308 PLL enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate and there is less than 50 µA of current draw. The PLL shuts down in two additional cases explained in Table Select Input Decoding.

Multiple MPC962308 devices can accept and distribute the same input clock throughout the system. In this situation, the difference between the output skews of two devices will be less than 700 ps.

The MPC962308 is available in five different configurations as shown in Table Available MPC962308 Configurations. In the MPC962308-1, the reference frequency is reproduced by the PLL and provided at the outputs. A high drive version of this configuration, the MPC962308-1H, is available to provide faster rise and fall times of the device.

The MPC962308-2 provides 2X and 1X the reference frequency at the output banks. In addition, the MPC962308-3 provides 4X and 2X the reference frequency at the output banks. The output banks driving the feedback will determine the different configurations of the above devices. The MPC962308-4 provides outputs 2X the reference frequency.The MPC962308-5H is a high drive version with outputs of REF/2.

The MPC962308 is fully V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines on the incident edge. Depending on the configuration, the device is offered in a 16-lead SOIC or 16-lead TSSOP package.

Motorola, Inc. 2004

For More Information On This Product, Go to:

Freescale Semiconductor, Inc...

Freescale Semiconductor, Inc.

MPC962308

Block Diagram

Extra Divider -3, -4 Extra Divider -5H

Select Input

Decoding

MUX /2

Extra Divider -2, -3

FBK CLKA1 CLKA2 CLKA3 CLKA4

CLKB1 CLKB2 CLKB3 CLKB4

Pin Configuration

SOIC/TSSOP Top View

REF 1

CLKA1 2

CLKA2 3 VDD 4 GND 5

CLKB1 6 CLKB2 7
16 FBK 15 CLKA4
14 CLKA3 13 VDD
Ordering Information Available
Ordering Code MPC962308D-1 MPC962308D-1R2 MPC962308D-1H MPC962308D-1HR2 MPC962308DT-1H MPC962308DT-1HR2 MPC962308D-2 MPC962308D-2R2
Ordering Information Planned
Ordering Code MPC962308D-3 MPC962308D-3R2 MPC962308D-4 MPC962308D-4R2 MPC962308D-5H MPC962308D-5HR2 MPC962308DT-5H MPC962308DT-5HR2

Package Name D16 DT16 D16

Package Type 16-pin 150-mil SOIC 16-pin 150-mil SOIC Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC Tape and Reel 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC Tape and Reel

Package Name D16 DT16

Package Type 16-pin 150-mil SOIC 16-pin 150-mil SOIC Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC Tape and Reel 16-pin 150-mil TSSOP 16-pin 150-mil TSSOP Tape and Reel

MOTOROLA

For More Informat7ion On This Product, Go to:

TIMING SOLUTIONS

Freescale Semiconductor, Inc.

MPC962308

PIN'S NUMBER

PIN 1 INDEX

PACKAGE DIMENSIONS

D SUFFIX 16 LEAD SOIC PACKAGE

CASE 751B-05 ISSUE K

M T A B

SEATING PLANE

NOTES DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.62MM.

SECTION A-A

Freescale Semiconductor, Inc...

TIMING SOLUTIONS

For More Informat8ion On This Product, Go to:

MOTOROLA

MPC962308

Freescale Semiconductor, Inc.

PACKAGE DIMENSIONS

DT SUFFIX 16 LEAD TSSOP PACKAGE

CASE 948F-01 ISSUE O
2X L/2

PIN 1 IDENT.
-T- SEATING

PLANE

K 16X REF M T U S V S

SECTION N-N

DETAIL E

DETAIL E

NOTES DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION MILLIMETER. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED PER SIDE. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED PER SIDE. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-.

MILLIMETERS

DIM MIN MAX

C ---

INCHES

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Datasheet ID: MPC962308DT-1H 635585