MPC9448FAR2

MPC9448FAR2 Datasheet

Order Number MPC9448/D Rev 3, 04/2003

Part	Datasheet
MPC9448FAR2	MPC9448FAR2 (pdf)

Related Parts	Information
MPC9448FA	MPC9448FA
MPC9448AC	MPC9448AC

PDF Datasheet Preview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer MPC9448 The MPC9448 is a 3.3V or 2.5V compatible, 1:12 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 ps, the device meets the needs of most demanding clock applications. • 12 LVCMOS compatible clock outputs • Selectable LVCMOS and differential LVPECL compatible clock inputs • Maximum clock frequency of 350 MHz • Maximum clock skew of 150 ps • Synchronous output stop in logic low state eliminates output runt pulses • output control • 3.3V or 2.5V power supply • Drives up to 24 series terminated clock lines • Ambient temperature range to +85°C • LQFP packaging • Supports clock distribution in networking, telecommunication and computing applications • Pin and function compatible to MPC948 LOW VOLTAGE 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER FA SUFFIX LQFP PACKAGE CASE 873A Functional Description The MPC9448 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. Each output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of terminated transmission lines on the incident edge each output is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock distribution systems. The MPC9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into mode. All inputs have an internal or resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of to +85°C. The MPC9448 is pin and function compatible but to the MPC948. Motorola, Inc. 2003 MPC9448 PCLK CCLK 0 CLK STOP CLK_SEL VCC CLK_STOP SYNC W all input resistors have a value of 25k 24 23 22 21 20 19 18 17 MPC9448 1 234 56 78 PCLK PCLK CCLK CLK_SEL CLK_STOP Figure Logic Diagram Figure Package Pinout Top View Table FUNCTION TABLE Control Default CLK_SEL OE PECL differential input selected Outputs disabled high-impedance state 1 CLK_STOP

PDF Datasheet Preview

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer

MPC9448

The MPC9448 is a 3.3V or 2.5V compatible, 1:12 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 ps, the device meets the needs of most demanding clock applications.
• 12 LVCMOS compatible clock outputs
• Selectable LVCMOS and differential LVPECL compatible clock inputs
• Maximum clock frequency of 350 MHz
• Maximum clock skew of 150 ps
• Synchronous output stop in logic low state eliminates output runt pulses
• output control
• 3.3V or 2.5V power supply
• Drives up to 24 series terminated clock lines
• Ambient temperature range to +85°C
• LQFP packaging
• Supports clock distribution in networking, telecommunication and
computing applications
• Pin and function compatible to MPC948

LOW VOLTAGE 3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER

FA SUFFIX LQFP PACKAGE

CASE 873A

Functional Description The MPC9448 is specifically designed to distribute LVCMOS
compatible clock signals up to a frequency of 350 MHz. Each output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of terminated transmission lines on the incident edge each output is capable of driving either one parallel terminated or two series terminated transmission lines.

Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock distribution systems. The MPC9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control will force the outputs into mode.

All inputs have an internal or resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of to +85°C. The MPC9448 is pin and function compatible but to the MPC948.

Motorola, Inc. 2003

MPC9448

PCLK

CCLK
0 CLK

STOP

CLK_SEL VCC

CLK_STOP

SYNC

W all input resistors have a value of 25k
24 23 22 21 20 19 18 17

MPC9448
1 234 56 78

PCLK

PCLK

CCLK

CLK_SEL

CLK_STOP

Figure Logic Diagram

Figure Package Pinout Top View

Table FUNCTION TABLE

Control

Default

CLK_SEL OE

PECL differential input selected

Outputs disabled high-impedance state 1

CLK_STOP

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Datasheet ID: MPC9448FAR2 635577