IDT71V3556S150BQ8

IDT71V3556S150BQ8 Datasheet

IDT71V3556S/XS IDT71V3558S/XS IDT71V3556SA/XSA IDT71V3558SA/XSA

Part	Datasheet
IDT71V3556S150BQ8	IDT71V3556S150BQ8 (pdf)

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IDT71V3558S100PFI	IDT71V3558S100PFI
IDT71V3558S100PF8	IDT71V3558S100PF8
IDT71V3558S100PF	IDT71V3558S100PF
IDT71V3558S100BQI8	IDT71V3558S100BQI8
IDT71V3558S100BQI	IDT71V3558S100BQI
IDT71V3558S133PF	IDT71V3558S133PF
IDT71V3558S100BQ	IDT71V3558S100BQ
IDT71V3558S200BQI8	IDT71V3558S200BQI8
IDT71V3558S100BG	IDT71V3558S100BG
IDT71V3558SA133BQ	IDT71V3558SA133BQ
IDT71V3558S133BQ	IDT71V3558S133BQ
IDT71V3558XS133PFI8	IDT71V3558XS133PFI8
IDT71V3558XS133PFI	IDT71V3558XS133PFI
IDT71V3558XS133PFGI8	IDT71V3558XS133PFGI8
IDT71V3558XS133PFGI	IDT71V3558XS133PFGI
IDT71V3558XS133PFG8	IDT71V3558XS133PFG8
IDT71V3558XS133PFG	IDT71V3558XS133PFG
IDT71V3558XS133PF8	IDT71V3558XS133PF8
IDT71V3558S200BQ8	IDT71V3558S200BQ8
IDT71V3558SA133BQ8	IDT71V3558SA133BQ8
IDT71V3558S200BQ	IDT71V3558S200BQ
IDT71V3558SA133BG8	IDT71V3558SA133BG8
IDT71V3558SA133BG	IDT71V3558SA133BG
IDT71V3558SA100BQ8	IDT71V3558SA100BQ8
IDT71V3558SA100BQ	IDT71V3558SA100BQ
IDT71V3558SA100BG8	IDT71V3558SA100BG8
IDT71V3558SA100BG	IDT71V3558SA100BG
IDT71V3558S200PF8	IDT71V3558S200PF8
IDT71V3558S200PF	IDT71V3558S200PF
IDT71V3558XS133PF	IDT71V3558XS133PF
IDT71V3558S166BG8	IDT71V3558S166BG8
IDT71V3558S133BG	IDT71V3558S133BG
IDT71V3558S133BG8	IDT71V3558S133BG8
IDT71V3558S133BGI	IDT71V3558S133BGI
IDT71V3558S133BGI8	IDT71V3558S133BGI8
IDT71V3558S133BQ8	IDT71V3558S133BQ8
IDT71V3558S100BG8	IDT71V3558S100BG8
IDT71V3558S133PF8	IDT71V3558S133PF8
IDT71V3558S133PFI	IDT71V3558S133PFI
IDT71V3558S200BQI	IDT71V3558S200BQI
IDT71V3558S166BG	IDT71V3558S166BG
IDT71V3558S100PFI8	IDT71V3558S100PFI8
IDT71V3558S166BGI	IDT71V3558S166BGI
IDT71V3558S166BGI8	IDT71V3558S166BGI8
IDT71V3558S166PF	IDT71V3558S166PF
IDT71V3558S166PF8	IDT71V3558S166PF8
IDT71V3558S166PFI	IDT71V3558S166PFI
IDT71V3558S166PFI8	IDT71V3558S166PFI8
IDT71V3558S200BG	IDT71V3558S200BG
IDT71V3558S200BG8	IDT71V3558S200BG8
IDT71V3558S133PFI8	IDT71V3558S133PFI8
IDT71V3556S133BQG	IDT71V3556S133BQG
IDT71V3556S100PF8	IDT71V3556S100PF8
IDT71V3556S100PFI	IDT71V3556S100PFI
IDT71V3556S166PF	IDT71V3556S166PF
IDT71V3556S100PFI8	IDT71V3556S100PFI8
IDT71V3556S133BG	IDT71V3556S133BG
IDT71V3556S133BG8	IDT71V3556S133BG8
IDT71V3556S166BG8	IDT71V3556S166BG8
IDT71V3556S166BGI	IDT71V3556S166BGI
IDT71V3556S166BGI8	IDT71V3556S166BGI8
IDT71V3556S133BGI	IDT71V3556S133BGI
IDT71V3556S133BGI8	IDT71V3556S133BGI8
IDT71V3556S133BQ	IDT71V3556S133BQ
IDT71V3556S100PF	IDT71V3556S100PF
IDT71V3556S166BQ	IDT71V3556S166BQ
IDT71V3556S166BG	IDT71V3556S166BG
IDT71V3556S133PF8	IDT71V3556S133PF8
IDT71V3556S166BQ8	IDT71V3556S166BQ8
IDT71V3556S166BQG	IDT71V3556S166BQG
IDT71V3556S133BQG8	IDT71V3556S133BQG8
IDT71V3556S133BQGI	IDT71V3556S133BQGI
IDT71V3556S133BQGI8	IDT71V3556S133BQGI8
IDT71V3556S133BQI	IDT71V3556S133BQI
IDT71V3556S133BQI8	IDT71V3556S133BQI8
IDT71V3556S166BQG8	IDT71V3556S166BQG8
IDT71V3556S166BQGI	IDT71V3556S166BQGI
IDT71V3556S166BQGI8	IDT71V3556S166BQGI8
IDT71V3556S133PF	IDT71V3556S133PF
IDT71V3556S166PF8	IDT71V3556S166PF8
IDT71V3556S133BQ8	IDT71V3556S133BQ8
IDT71V3556S100BQ8	IDT71V3556S100BQ8
IDT71V3556S150BG8	IDT71V3556S150BG8
IDT71V3556S100BQ	IDT71V3556S100BQ
IDT71V3556S100BGI8	IDT71V3556S100BGI8
IDT71V3556S100BGI	IDT71V3556S100BGI
IDT71V3556S100BQI8	IDT71V3556S100BQI8
IDT71V3556S133PFI8	IDT71V3556S133PFI8
IDT71V3556S166PFI	IDT71V3556S166PFI
IDT71V3556S150BQ	IDT71V3556S150BQ
IDT71V3556S100BG8	IDT71V3556S100BG8
IDT71V3556S150BG	IDT71V3556S150BG
IDT71V3556S150PF	IDT71V3556S150PF
IDT71V3556S166PFI8	IDT71V3556S166PFI8
IDT71V3556S100BQG	IDT71V3556S100BQG
IDT71V3556S133PFI	IDT71V3556S133PFI
IDT71V3556S100BG	IDT71V3556S100BG
IDT71V3556S100BQG8	IDT71V3556S100BQG8
IDT71V3556S100BQGI	IDT71V3556S100BQGI
IDT71V3556S100BQGI8	IDT71V3556S100BQGI8
IDT71V3556S150PF8	IDT71V3556S150PF8
IDT71V3558S100BQ8	IDT71V3558S100BQ8
IDT71V3556S100BQI	IDT71V3556S100BQI

PDF Datasheet Preview
128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs IDT71V3556S/XS IDT71V3558S/XS IDT71V3556SA/XSA IDT71V3558SA/XSA 128K x 36, 256K x 18 memory configurations Supports high performance system speed - 200 MHz ns Clock-to-Data Access ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W READ/WRITE control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications 4-word burst capability interleaved or linear Individual byte write BW1 - BW4 control May tie active Three chip enables for simple depth expansion 3.3V power supply ±5% , 3.3V I/O Supply VDDQ Optional- Boundary Scan JTAG Interface IEEE compliant Packaged in a JEDEC standard 100-pin plastic thin quad flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball grid array fBGA The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit Megabit synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71V3556/58 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable CEN pin allows operation of the IDT71V3556/58 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values. There are three chip enable pins CE1, CE2, CE2 that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers reads or writes will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated. Pin Description Summary A0-A17 CE1, CE2, CE2 OE R/W CEN BW1, BW2, BW3, BW4 CLK ADV/LD LBO TMS TDI TCK TDO TRST ZZ I/O0-I/O31, I/OP1-I/OP4 VDD, VDDQ VSS Address Inputs Chip Enables Output Enable Read/Write Signal Clock Enable Individual Byte Write Selects Clock Advance burst address / Load new address Linear / Interleaved Burst Order Test Mode Select Test Data Input Test Clock Test Data Output JTAG Reset Optional Sleep Mode Data Input / Output Core Power, I/O Power Ground 2006 Integrated Device Technology, Inc. Input Output Input I/O Supply Synchronous Asynchronous Synchronous N/A Synchronous Static Synchronous N/A Synchronous Asynchronous Synchronous Static 5281 tbl 01 FEBRUARY 2009 DSC-5281/09 IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Description continued The IDT71V3556/58 has an on-chip burst counter. In the burst mode, the IDT71V3556/58 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new Pin Definition 1 Pin Function I/O Active Description external address ADV/LD = LOW or increment the internal burst counter ADV/LD = HIGH . The IDT71V3556/58 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and a 165 fine pitch ball grid array fBGA . A0-A17 Address Inputs Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD low, CEN low, and true chip enables. ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it Ordering Information IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Datasheet Document History 6/30/99 8/23/99 10/4/99 12/31/99 04/30/00 05/26/00 07/26/00 10/25/00 1/24/02 9/30 /04 10/18/06 02/20/09 Pg. 4, 5 Pg. 6 Pg. 14 Pg. 15 Pg. 22 Pg. 24 Pg. 14 Pg. 15 Pg. 5, 6 Pg. 6 Pg. 5,6, 7 Pg. 21 Pg. 23 Pg. 5-8 Pg. 8 Pg. 23 Pg. 8 Pg. 1-8, 15,22,23,27 Pg. 7 Pg. 27 Pg. 1, 26 Pg. 27 Removed "IDT" from orderable part number. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Rd San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 800-345-7015 or 408/284-4555 The IDT logo is a registered trademark of Integrated Device Technology, Inc. and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

PDF Datasheet Preview

128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs

IDT71V3556S/XS IDT71V3558S/XS IDT71V3556SA/XSA IDT71V3558SA/XSA
128K x 36, 256K x 18 memory configurations Supports high performance system speed - 200 MHz
ns Clock-to-Data Access ZBTTM Feature - No dead cycles between write and read
cycles Internally synchronized output buffer enable eliminates the
need to control OE Single R/W READ/WRITE control pin Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications 4-word burst capability interleaved or linear Individual byte write BW1 - BW4 control May tie active Three chip enables for simple depth expansion 3.3V power supply ±5% , 3.3V I/O Supply VDDQ Optional- Boundary Scan JTAG Interface IEEE
compliant Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball grid array fBGA

The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit Megabit synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write.

The IDT71V3556/58 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time.

A Clock Enable CEN pin allows operation of the IDT71V3556/58 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values.

There are three chip enable pins CE1, CE2, CE2 that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers reads or writes will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated.

Pin Description Summary

A0-A17 CE1, CE2, CE2 OE R/W CEN BW1, BW2, BW3, BW4 CLK ADV/LD LBO TMS TDI TCK TDO TRST ZZ I/O0-I/O31, I/OP1-I/OP4 VDD, VDDQ VSS

Address Inputs Chip Enables Output Enable Read/Write Signal Clock Enable Individual Byte Write Selects Clock Advance burst address / Load new address Linear / Interleaved Burst Order Test Mode Select Test Data Input Test Clock Test Data Output JTAG Reset Optional Sleep Mode Data Input / Output Core Power, I/O Power Ground
2006 Integrated Device Technology, Inc.

Input Output Input I/O Supply

Synchronous Asynchronous Synchronous

N/A Synchronous

Static Synchronous

N/A Synchronous Asynchronous Synchronous

Static
5281 tbl 01

FEBRUARY 2009

DSC-5281/09

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Description continued

The IDT71V3556/58 has an on-chip burst counter. In the burst mode, the IDT71V3556/58 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new

Pin Definition 1

Pin Function

I/O Active Description
external address ADV/LD = LOW or increment the internal burst counter ADV/LD = HIGH .

The IDT71V3556/58 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and a 165 fine pitch ball grid array fBGA .

A0-A17

Address Inputs

Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD low, CEN low, and true chip enables.

ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it
Ordering Information

IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Datasheet Document History
6/30/99 8/23/99
10/4/99 12/31/99 04/30/00
05/26/00 07/26/00 10/25/00 1/24/02 9/30 /04 10/18/06 02/20/09

Pg. 4, 5 Pg. 6 Pg. 14 Pg. 15

Pg. 22 Pg. 24 Pg. 14 Pg. 15

Pg. 5, 6

Pg. 6 Pg. 5,6, 7 Pg. 21

Pg. 23 Pg. 5-8 Pg. 8 Pg. 23

Pg. 8 Pg. 1-8, 15,22,23,27 Pg. 7

Pg. 27 Pg. 1, 26 Pg. 27
Removed "IDT" from orderable part number.

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Rd San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support 800-345-7015 or 408/284-4555

The IDT logo is a registered trademark of Integrated Device Technology, Inc. and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT71V3556S150BQ8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT71V3556S150BQ8 637334