MPC9350FA

MPC9350FA Datasheet

MPC9350 Rev 6, 4/2005

Part	Datasheet
MPC9350FA	MPC9350FA (pdf)

Related Parts	Information
MPC9350AC	MPC9350AC

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Freescale Semiconductor Technical Data Low Voltage PLL Clock Driver The MPC9350 is a V and V compatible, PLL-based clock generator targeted for high performance clock distribution systems. With output frequencies of up to 200 MHz and maximum output skews of 150 ps, the MPC9350 is ideal for the most demanding clock tree designs. The device offers 9 low skew clock outputs, with each one configurable to support the clocking needs of the various high-performance microprocessors, including the PowerQUICC II integrated communication microprocessor. The extended temperature range of the MPC9350 supports telecommunication and networking requirements. The device employs a fully differential PLL design to minimize cycle-to-cycle and long-term jitter. MPC9350 LOW VOLTAGE V AND V PLL CLOCK GENERATOR • 9 output LVCMOS PLL clock generator • 25 200 MHz output frequency range • V and V compatible • Compatible to various microprocessors such as PowerQuicc II • Supports networking, telecommunications and computer applications • Fully integrated PLL • Configurable outputs divide-by-2, 4 and 8 of VCO frequency • Selectable output to input frequency ratio of 8:1, 4:1, 2:1 or 1:1 • Oscillator or crystal reference inputs • Internal PLL feedback • Output disable • PLL enable/disable • Low skew characteristics maximum 150 ps output-to-output • 32-lead LQFP package • 32-lead Pb-free Package Available • Temperature range to +85°C FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-03 Functional Description The MPC9350 generates high frequency clock signals and provides nine exact frequency-multiplied copies of the reference clock signal. The internal PLL allows the MPC9350 to operate in frequency locked condition and to multiply the input reference clock. The reference clock frequency and the divider in the internal feedback path determine the VCO frequency. Two selectable PLL feedback frequency ratios are available on the MPC9350 to provide input frequency range flexibility. The FBSEL pin selects between divide-by-16 or divide-by-32 of the VCO frequency for PLL feedback. This feedback divider must be selected to match the VCO frequency range. With the available feedback output dividers, the internal VCO of the MPC9350 is running at either 16x or 32x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 16:1, 8:1, 4:1 and The REF_SEL pin selects the crystal oscillator input or the LVCMOS compatible reference input TCLK . TCLK also provides an external test clock in static test mode when the PLL enable pin PLL_EN is pulled to logic low state. In test mode, the selected input reference clock is routed directly to the output dividers without using the PLL. The test mode is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin logic high state . In PLL mode, deasserting OE maintains PLL lock due to the internal feedback path. The MPC9350 is fully V and V compatible and requires no external loop filter components. The on-chip crystal oscillator requires no external components beyond a series resonant crystal. All inputs except the crystal oscillator interface accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9350 outputs can drive one or two traces giving the device an effective fanout of The device is packaged in a 7x7 mm2 32-lead LQFP package. Freescale Semiconductor, Inc., All rights reserved. XTAL1 XTAL2 Ref PLL TCLK Pulldown REF_SEL Pulldown ÷16 200 400 MHz ÷32 FBSEL PLL_EN FSELA FSELB FSELC FSELD Pulldown Pullup Pulldown Pulldown QC0 0 QD1 0 1 QD3 Pulldown Figure MPC9350 Logic Diagram QC0 VCCO QC1 GND QD0 VCCO QD1 GND MPC9350 2 GND QB VCCO QA GND TCLK PLL_EN REF_SEL 24 23 22 21 20 19 18 17 MPC9350 12345678 QD2 VCCO QD3 GND QD4 VCCO OE XTAL2 VCCA FBSEL FSELA FSELB FSELC FSELD GND XTAL1

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Freescale Semiconductor Technical Data

Low Voltage PLL Clock Driver

The MPC9350 is a V and V compatible, PLL-based clock generator targeted for high performance clock distribution systems. With output frequencies of up to 200 MHz and maximum output skews of 150 ps, the MPC9350 is ideal for the most demanding clock tree designs. The device offers 9 low skew clock outputs, with each one configurable to support the clocking needs of the various high-performance microprocessors, including the PowerQUICC II integrated communication microprocessor. The extended temperature range of the MPC9350 supports telecommunication and networking requirements. The device employs a fully differential PLL design to minimize cycle-to-cycle and long-term jitter.

MPC9350

LOW VOLTAGE V AND V PLL CLOCK GENERATOR
• 9 output LVCMOS PLL clock generator
• 25 200 MHz output frequency range
• V and V compatible
• Compatible to various microprocessors such as PowerQuicc II
• Supports networking, telecommunications and computer applications
• Fully integrated PLL
• Configurable outputs divide-by-2, 4 and 8 of VCO frequency
• Selectable output to input frequency ratio of 8:1, 4:1, 2:1 or 1:1
• Oscillator or crystal reference inputs
• Internal PLL feedback
• Output disable
• PLL enable/disable
• Low skew characteristics maximum 150 ps output-to-output
• 32-lead LQFP package
• 32-lead Pb-free Package Available
• Temperature range to +85°C

FA SUFFIX 32-LEAD LQFP PACKAGE

CASE 873A-03

AC SUFFIX 32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE CASE 873A-03

Functional Description

The MPC9350 generates high frequency clock signals and provides nine exact frequency-multiplied copies of the reference clock signal. The internal PLL allows the MPC9350 to operate in frequency locked condition and to multiply the input reference clock. The reference clock frequency and the divider in the internal feedback path determine the VCO frequency. Two selectable PLL feedback frequency ratios are available on the MPC9350 to provide input frequency range flexibility. The FBSEL pin selects between divide-by-16 or divide-by-32 of the VCO frequency for PLL feedback. This feedback divider must be selected to match the VCO frequency range. With the available feedback output dividers, the internal VCO of the MPC9350 is running at either 16x or 32x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 16:1, 8:1, 4:1 and The REF_SEL pin selects the crystal oscillator input or the LVCMOS compatible reference input TCLK . TCLK also provides an external test clock in static test mode when the PLL enable pin PLL_EN is pulled to logic low state. In test mode, the selected input reference clock is routed directly to the output dividers without using the PLL. The test mode is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by deasserting the OE pin logic high state . In PLL mode, deasserting OE maintains PLL lock due to the internal feedback path. The MPC9350 is fully V and V compatible and requires no external loop filter components. The on-chip crystal oscillator requires no external components beyond a series resonant crystal. All inputs except the crystal oscillator interface accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9350 outputs can drive one or two traces giving the device an effective fanout of The device is packaged in a 7x7 mm2 32-lead LQFP package.

Freescale Semiconductor, Inc., All rights reserved.

XTAL1 XTAL2

Ref PLL

TCLK

Pulldown

REF_SEL

Pulldown
÷16
200 400 MHz
÷32

FBSEL PLL_EN FSELA FSELB FSELC FSELD

Pulldown Pullup Pulldown

Pulldown

QC0 0

QD1 0
1 QD3

Pulldown

Figure MPC9350 Logic Diagram

QC0 VCCO QC1 GND QD0 VCCO QD1 GND

MPC9350 2

GND QB

VCCO QA

GND TCLK PLL_EN REF_SEL
24 23 22 21 20 19 18 17

MPC9350
12345678

QD2 VCCO QD3 GND QD4 VCCO OE XTAL2

VCCA FBSEL FSELA FSELB FSELC FSELD

GND XTAL1

More datasheets: 03450711X | 03450603X | 03450601X | 03450611X | 03450903X | 03450612X | 03450701X | 03450613X | 308N500K | MPC9350AC

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Datasheet ID: MPC9350FA 635563