MPC9331FAR2

MPC9331FAR2 Datasheet

MPC9331 Rev. 7, 1/2005

Part	Datasheet
MPC9331FAR2	MPC9331FAR2 (pdf)

Related Parts	Information
MPC9331AC	MPC9331AC
MPC9331FA	MPC9331FA

PDF Datasheet Preview
Freescale Semiconductor Technical Data V 1:6 LVCMOS PLL Clock Generator MPC9331 The MPC9331 is a V compatible, 1:6 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking, and computing applications. With output frequencies up to 240 MHz and output skews less than 150 ps, the device meets the needs of most the demanding clock applications. The MPC9331 is specified for the temperature range of 0°C to +70°C. • 1:6 PLL based low-voltage clock generator • V power supply • Generates clock signals up to 240 MHz • Maximum output skew of 150 ps • Differential LVPECL reference clock input • Alternative LVCMOS PLL reference clock input • Internal and external PLL feedback • Supports zero-delay operation in external feedback mode • PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3 or x/4 • Synchronous output clock stop in logic low eliminates output runt pulses • Power_down feature reduces output clock frequency • Drives up to 12 clock lines • 32-lead LQFP packaging • 32-lead Pb-free Package Available • Ambient temperature range 0°C to +70°C • Internal Power-Up Reset • Pin and function compatible to the MPC931 LOW VOLTAGE V LVCMOS 1:6 CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-03 Functional Description The MPC9331 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9331 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback configuration and with the available post-PLL dividers divide-by-2, divide-by-4, and divide-by-6 , the internal VCO of the MPC9331 is running at either 2x, 4x, 6x, 8x, or 12x of the reference clock frequency. In internal feedback configuration divide-by-8 the internal VCO is running 8x of the reference frequency. The frequency of the QA, QB, QC output banks is a division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB, and FSELC pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4. The REF_SEL pin selects the differential LVPECL or the LVCMOS compatible input as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled high-impedance by deasserting the OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9331 output clock stop control allows the outputs to start and stop synchronously in logic low state, without the potential generation of runt pulses. The MPC9331 is fully V compatible and requires no external loop filter components. The inputs except PCLK accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9331 outputs can drive one or two traces giving the devices an effective fanout of The device is packaged in a 7x7 mm2 32-lead LQFP package. Freescale Semiconductor, Inc., All rights reserved. VCC 3 x 25 K PCLK CCLK REF_SEL 200 480 MHz FB_IN FB_SEL PWR_DN 25k VCC 25k VCC 25k FB ÷8 Bank A Stop Bank B Stop Bank C Stop PLL_EN FSELA FSELB FSELC 3 x 25 K Power_On Reset 3 x 25 K CLK_STOP0 CLK_STOP1 OE/MR Figure MPC9331 Logic Diagram

PDF Datasheet Preview

Freescale Semiconductor Technical Data

V 1:6 LVCMOS PLL Clock Generator

MPC9331

The MPC9331 is a V compatible, 1:6 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking, and computing applications. With output frequencies up to 240 MHz and output skews less than 150 ps, the device meets the needs of most the demanding clock applications. The MPC9331 is specified for the temperature range of 0°C to +70°C.
• 1:6 PLL based low-voltage clock generator
• V power supply
• Generates clock signals up to 240 MHz
• Maximum output skew of 150 ps
• Differential LVPECL reference clock input
• Alternative LVCMOS PLL reference clock input
• Internal and external PLL feedback
• Supports zero-delay operation in external feedback mode
• PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3
or x/4
• Synchronous output clock stop in logic low eliminates output runt pulses
• Power_down feature reduces output clock frequency
• Drives up to 12 clock lines
• 32-lead LQFP packaging
• 32-lead Pb-free Package Available
• Ambient temperature range 0°C to +70°C
• Internal Power-Up Reset
• Pin and function compatible to the MPC931

LOW VOLTAGE V LVCMOS 1:6 CLOCK GENERATOR

FA SUFFIX 32-LEAD LQFP PACKAGE

CASE 873A-03

AC SUFFIX 32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE CASE 873A-03

Functional Description

The MPC9331 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9331 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback configuration and with the available post-PLL dividers divide-by-2, divide-by-4, and divide-by-6 , the internal VCO of the MPC9331 is running at either 2x, 4x, 6x, 8x, or 12x of the reference clock frequency. In internal feedback configuration divide-by-8 the internal VCO is running 8x of the reference frequency. The frequency of the QA, QB, QC output banks is a division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB, and FSELC pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4.

The REF_SEL pin selects the differential LVPECL or the LVCMOS compatible input as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled high-impedance by deasserting the OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9331 output clock stop control allows the outputs to start and stop synchronously in logic low state, without the potential generation of runt pulses.

The MPC9331 is fully V compatible and requires no external loop filter components. The inputs except PCLK accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9331 outputs can drive one or two traces giving the devices an effective fanout of The device is packaged in a 7x7 mm2 32-lead LQFP package.

Freescale Semiconductor, Inc., All rights reserved.

VCC 3 x 25 K

PCLK

CCLK

REF_SEL
200 480 MHz

FB_IN FB_SEL PWR_DN
25k VCC 25k

VCC 25k

FB ÷8

Bank A

Stop

Bank B

Stop

Bank C

Stop

PLL_EN

FSELA

FSELB

FSELC
3 x 25 K

Power_On Reset
3 x 25 K

CLK_STOP0

CLK_STOP1 OE/MR

Figure MPC9331 Logic Diagram

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MPC9331FAR2 Datasheet file may be downloaded here without warranties.

Datasheet ID: MPC9331FAR2 635562