MPC9230AC

MPC9230AC Datasheet

MPC9230 Rev. 5, 08/2005

Part	Datasheet
MPC9230AC	MPC9230AC (pdf)

Related Parts	Information
MPC9230FN	MPC9230FN
MPC9230FA	MPC9230FA

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Freescale Semiconductor Technical Data 800 MHz Low Voltage PECL Clock Synthesizer MPC9230 The MPC9230 is a V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 50 MHz to 800 MHz 1 and the support of differential PECL output signals the device meets the needs of the most demanding clock applications. 800 MHz LOW VOLTAGE CLOCK SYNTHESIZER Features • 50 MHz to 800 MHz 1 synthesized clock output signal • Differential PECL output • LVCMOS compatible control inputs • On-chip crystal oscillator for reference frequency generation • Alternative LVCMOS compatible reference clock input • V power supply • Fully integrated PLL • Minimal frequency overshoot • Serial 3-wire programming interface • Parallel programming interface for power-up • 32-lead LQFP and 28-lead PLCC packaging • 32-lead and 28-lead Pb-free package available • SiGe Technology • Ambient temperature range -40°C to +85°C • Pin and function compatible to the MC12430 Functional Description FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-02 EI SUFFIX 28-LEAD PLCC PACKAGE Pb-FREE PACKAGE CASE 776-02 FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz. 1 Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be times the reference frequency by adjusting the VCO control voltage. Note that for some values of M either too high or too low the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range 800 to 1600 MHz 1 . The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios 1, 2, 4, or This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to VCC V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs and prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. The VCO frequency range of MHz is available at an ambient temperature range of 0 to 70°C. At to +85°C, the VCO frequency output frequency is limited to max. 1500 MHz 750 MHz . Freescale Semiconductor, Inc., All rights reserved. XTAL_IN XTAL_OUT FREF_EXT XTAL_SEL P_LOAD S_LOAD S_DATA S_CLOCK M[0:8] N[1:0] XTAL 10 20 MHz ÷16 800 1800 MHz ÷1 11 ÷2 00 ÷4 01 ÷8 10 ÷0 TO ÷511 9-BIT M-Divider M-Latch LE Bits 5-13 N-Latch Bits 3-4 14-Bit Shift Register Figure MPC9230 Logic Diagram

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Freescale Semiconductor Technical Data
800 MHz Low Voltage PECL Clock Synthesizer

MPC9230

The MPC9230 is a V compatible, PLL based clock synthesizer targeted for
high performance clock generation in mid-range to high-performance telecom,
networking and computing applications. With output frequencies from 50 MHz to 800 MHz 1 and the support of differential PECL output signals the device meets
the needs of the most demanding clock applications.
800 MHz LOW VOLTAGE CLOCK SYNTHESIZER

Features
• 50 MHz to 800 MHz 1 synthesized clock output signal
• Differential PECL output
• LVCMOS compatible control inputs
• On-chip crystal oscillator for reference frequency generation
• Alternative LVCMOS compatible reference clock input
• V power supply
• Fully integrated PLL
• Minimal frequency overshoot
• Serial 3-wire programming interface
• Parallel programming interface for power-up
• 32-lead LQFP and 28-lead PLCC packaging
• 32-lead and 28-lead Pb-free package available
• SiGe Technology
• Ambient temperature range -40°C to +85°C
• Pin and function compatible to the MC12430

Functional Description

FN SUFFIX 28-LEAD PLCC PACKAGE

CASE 776-02

EI SUFFIX 28-LEAD PLCC PACKAGE

Pb-FREE PACKAGE CASE 776-02

FA SUFFIX 32-LEAD LQFP PACKAGE

CASE 873A-04

AC SUFFIX 32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE CASE 873A-04

The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz. 1 Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency.

The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be times the reference frequency by adjusting the VCO control voltage. Note that for some values of M either too high or too low the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range 800 to 1600 MHz 1 . The M-value must be programmed by the serial or parallel interface.

The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios 1, 2, 4, or This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 to VCC V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter.

The configuration logic has two sections serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs and prevent the LVCMOS compatible control inputs from floating.

The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.

The VCO frequency range of MHz is available at an ambient temperature range of 0 to 70°C. At to +85°C, the VCO frequency output frequency is limited to max. 1500 MHz 750 MHz .

Freescale Semiconductor, Inc., All rights reserved.

XTAL_IN XTAL_OUT FREF_EXT

XTAL_SEL

P_LOAD S_LOAD

S_DATA S_CLOCK

M[0:8] N[1:0]

XTAL 10 20 MHz
÷16
800 1800 MHz
÷1 11 ÷2 00 ÷4 01 ÷8 10
÷0 TO ÷511 9-BIT M-Divider

M-Latch LE

Bits 5-13

N-Latch

Bits 3-4
14-Bit Shift Register

Figure MPC9230 Logic Diagram

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Datasheet ID: MPC9230AC 635557