MPC9229FA

MPC9229FA Datasheet

Order Number MPC9229/D Rev 1 03/2003

Part	Datasheet
MPC9229FA	MPC9229FA (pdf)

Related Parts	Information
MPC9229FN	MPC9229FN
MPC9229AC	MPC9229AC

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MOTOROLA SEMICONDUCTOR TECHNFIrCeAeLsDcAaTAle Semiconductor, Inc. Freescale Semiconductor, Inc... 400 MHz Low Voltage PECL Clock Synthesizer MPC9229 The MPC9229 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 25 MHz to 400 MHz and the support of differential PECL output signals the device meets the needs of the most demanding clock applications. 400 MHZ LOW VOLTAGE CLOCK SYNTHESIZER • 25 MHz to 400 MHz synthesized clock output signal • Differential PECL output • LVCMOS compatible control inputs • On-chip crystal oscillator for reference frequency generation • 3.3V power supply • Fully integrated PLL • Minimal frequency overshoot • Serial 3-wire programming interface • Parallel programming interface for power-up • 32 lead LQFP and 28 PLCC packaging • SiGe Technology • Ambient temperature range 0°C to +70°C • Pin and function compatible to the MC12429 Functional Description The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency. FN SUFFIX 28--LEAD PLCC PACKAGE CASE 776 FA SUFFIX 32 LEAD LQFP PACKAGE CASE 873A The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be times the reference frequency by adjusting the VCO control voltage. Note that for some values of M either too high or too low the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range 800 to 1600 MHz . The M-value must be programmed by the serial or parallel interface. The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division ratios 1, 2, 4, or This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated to VCC 2.0V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating. The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output. Motorola, Inc. 2003 For More Information On This Product, Go to: MPC9229 Freescale Semiconductor, Inc. XTAL_IN XTAL_OUT P_LOAD S_LOAD S_DATA S_CLOCK M[0:8] N[1:0] XTAL ÷16 10 -- 20 MHz PLL 800-1600 MHz ÷1 00 ÷2 01 ÷4 10 ÷8 11 OE Sync VCC LE ÷0 to ÷511 9-Bit M-Divider M-Latch Bit 5-13

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MOTOROLA

SEMICONDUCTOR

TECHNFIrCeAeLsDcAaTAle

Semiconductor,

Inc.

Freescale Semiconductor, Inc...
400 MHz Low Voltage PECL Clock Synthesizer

MPC9229

The MPC9229 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. With output frequencies from 25 MHz to 400 MHz and the support of differential PECL output signals the device meets the needs of the most demanding clock applications.
400 MHZ LOW VOLTAGE CLOCK SYNTHESIZER
• 25 MHz to 400 MHz synthesized clock output signal
• Differential PECL output
• LVCMOS compatible control inputs
• On-chip crystal oscillator for reference frequency generation
• 3.3V power supply
• Fully integrated PLL
• Minimal frequency overshoot
• Serial 3-wire programming interface
• Parallel programming interface for power-up
• 32 lead LQFP and 28 PLCC packaging
• SiGe Technology
• Ambient temperature range 0°C to +70°C
• Pin and function compatible to the MC12429

Functional Description The internal crystal oscillator uses the external quartz crystal as the
basis of its frequency reference. The frequency of the internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency.

FN SUFFIX 28--LEAD PLCC PACKAGE

CASE 776

FA SUFFIX 32 LEAD LQFP PACKAGE

CASE 873A

The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be times the reference frequency by adjusting the VCO control voltage. Note that for some values of M either too high or too low the PLL will not achieve phase lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range 800 to 1600 MHz . The M-value must be programmed by the serial or parallel interface.

The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios 1, 2, 4, or This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated to VCC 2.0V. The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.

The configuration logic has two sections serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes valid. On the transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control inputs from floating.

The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configuration latches will capture the value of the shift register on the edge of the S_LOAD input. See the programming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.

Motorola, Inc. 2003

For More Information On This Product, Go to:

MPC9229

Freescale Semiconductor, Inc.

XTAL_IN XTAL_OUT

P_LOAD S_LOAD

S_DATA S_CLOCK

M[0:8] N[1:0]

XTAL
÷16
10 -- 20 MHz

PLL 800-1600 MHz
÷1 00 ÷2 01 ÷4 10 ÷8 11

OE Sync

VCC LE
÷0 to ÷511 9-Bit M-Divider

M-Latch

Bit 5-13

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Datasheet ID: MPC9229FA 635556