MPC852TVR66

MPC852TVR66 Datasheet

MPC852TEC Rev. 01/2005

Part	Datasheet
MPC852TVR66	MPC852TVR66 (pdf)

Related Parts	Information
MPC852TVR100	MPC852TVR100

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Freescale Semiconductor Technical Data MPC852T Hardware Specifications This document contains detailed information for the MPC852T about power considerations, DC/AC electrical characteristics, AC timing specifications, and pertinent electrical and physical characteristics of the MPC852T. For information about functional characteristics of the processor, refer to the MPC866 PowerQUICC Family Users Manual MPC866UM . The MPC852T contains a PowerPCTM processor core. The MPC852T PowerQUICCTM is a 0.18-micron derivative of the MPC860 PowerQUICC family, and can operate up to 100 MHz on the MPC8xx core with a 66-MHz external bus. The MPC852T has a V core and a V I/O operation with 5-V TTL compatibility. The MPC852T integrated communications controller is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in Ethernet control applications, including CPE equipment, Ethernet routers and hubs, VoIP clients, and WiFi access points. The MPC852T is a PowerPC architecture-based derivative of the Motorola MPC860 Quad Integrated Communications Controller PowerQUICC . The CPU on the MPC852T is the MPC8xx core, a 32-bit microprocessor that implements the PowerPC architecture, incorporating memory management units MMUs and instruction and data caches. The MPC852T is the subset of this family of devices. Freescale Semiconductor, Inc., All rights reserved. 2 Features The MPC852T is comprised of three modules that each use the 32-bit internal bus the MPC8xx core, the system integration unit SIU , and the communication processor module CPM . Figure 1 shows the MPC852T block diagram. The following list summarizes the key MPC852T features • Embedded MPC8xx core up to 100 MHz • Maximum frequency operation of the external bus is 66 MHz The 50 MHz / 66 MHz core frequencies support both 1:1 and 2:1 modes. The 80 MHz / 100 MHz core frequencies support 2:1 mode only. • Single-issue, 32-bit core compatible with the PowerPC architecture definition with 32-bit general-purpose registers GPRs The core performs branch prediction with conditional prefetch, without conditional execution. 4-Kbyte data cache and 4-Kbyte instruction cache 4-Kbyte instruction cache is two-way, set-associative with 128 sets. 4-Kbyte data cacheis two-way, set-associative with 128 sets. Cache coherency for both instruction and data caches is maintained on 128-bit 4-word cache blocks. Caches are physically addressed, implement a least recently used LRU replacement algorithm, and are lockable on a cache block basis. MMUs with 32-entry TLB, fully associative instruction, and data TLBs MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes 16 virtual address spaces, and 16 protection groups • Up to 32-bit data bus dynamic bus sizing for 8, 16, and 32 bits • 32 address lines • Memory controller eight banks Contains complete dynamic RAM DRAM controller Each bank can be a chip select or RAS to support a DRAM bank Up to 30 wait states programmable per memory bank Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices DRAM controller-programmable to support most size and speed memory interfaces Four CAS lines, four WE lines, and one OE line Boot chip-select available at reset options for 8-, 16-, or 32-bit memory Variable block sizes 32 Mbytes Selectable write protection On-chip bus arbitration logic • Fast Ethernet Controller FEC • General-purpose timers Two 16-bit timers or one 32-bit timer Gate mode can enable or disable counting. Interrupt can be masked on reference match and event capture. Freescale Semiconductor • System integration unit SIU Bus monitor Software watchdog Periodic interrupt timer PIT Clock synthesizer Decrementer and time base Reset controller IEEE test access port JTAG • Interrupts Seven external interrupt request IRQ lines Seven port pins with interrupt capability Eighteen internal interrupt sources Programmable priority between SCCs Programmable highest-priority request • Communications processor module CPM RISC controller Communication-specific commands for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and RESTART TRANSMIT Supports continuous mode transmission and reception on all serial channels 8-Kbytes of dual-port RAM 8 serial DMA SDMA channels Three parallel I/O registers with open-drain capability • Two baud rate generators Independent can be connected toany SCC3/4 or SMC1 Allows changes during operation Autobaud support option • Two SCCs serial communication controllers Ethernet/IEEE optional on SCC3 & SCC4, supporting full 10-Mbps operation HDLC/SDLC HDLC bus implements an HDLC-based local area network LAN Universal asynchronous receiver transmitter UART Totally transparent bit streams Totally transparent frame-based with optional cyclic redundancy check CRC • One SMC serial management channels UART • One SPI serial peripheral interface Supports master and slave modes Supports multimaster operation on the same bus • PCMCIA interface Master socket interface, release compliant Freescale Semiconductor Supports one independent PCMCIA socket 8-memory or I/O windows supported • Debug interface Eight comparators four operate on instruction address, two operate on data address, and two operate on data Supports conditions = < > Each watchpoint can generate a break point internally. • Normal high and normal low power modes to conserve power • V Core and V I/O operation with 5-V TTL compatibility. Refer to Table 5 for a listing of the 5-V Tolerant pins. Embedded MPC8xx Processor Core Instruction 4-Kbyte Bus Instruction Cache Instruction MMU 32-Entry ITLB Load/Store 4-Kbyte Data Cache Data MMU 32-Entry DTLB Fast Ethernet Controller DMAs Unified Bus System Interface Unit SIU Memory Controller Internal External Bus Interface Bus Interface Unit Unit System Functions PCMCIA-ATA Interface FIFOs 10/100 Base-T Media Access Control Parallel I/O 2 Baud Rate Generators Mechanical Data and Ordering Information 16 Mechanical Data and Ordering Information Table 29 identifies the packages and operating frequencies orderable for the MPC852T. Table MPC852T Package/Frequency Orderable Package Type Plastic ball grid array VR and ZT suffix Plastic ball grid array CVR suffix Temperature Tj 0°C to 95°C 40°C to 100°C Frequency MHz 50 66 80 100 66 Order Number MPC852TVR50 MPC852TZT50 MPC852TVR66 MPC852TZT66 MPC852TVR80 MPC852TZT80 MPC852TVR100 MPC852TZT100 Pin Assignments The following sections give the pinout and pin listing for the JEDEC Compliant and the non-JEDEC versions of the 16 x 16 PBGA package. Freescale Semiconductor Mechanical Data and Ordering Information The JEDEC Compliant Pinout Figure 62 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the MPC866 PowerQUICC Family User’s Manual. NOTE This is the top view of the device. A N/C CS1 CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7 A2 A1 N/C B WR CS0 CE2_A GPL_A3 WE3 MII_CRS BS_A3 A22 A30 A29 A27 A13 A9 A6 A0 N/C VDDL GPL_A4 CS3 CS5 GPL_A0 WE1 BS_A2 A26 A25 A21 A17 A12 A8 C A3 N/C PC15 D BDIP BI CS2 CS6 OE WE0 BS_A1 A31 A24 A20 A15 A10 A4 N/C PB29 VDDL E BR TS TEA GPL_A5 CE_1A CS4 TSIZ1 TSIZ0 A16 A11 A5 N/C PB31 PC13 PC12 PA11 CR MII_COL BB TA F PB30 TDO TMS TRST VFLS_1 RSV BURST BG G PB28 TDI VDDL MDIO ALE_A DSCK VFLS_0 FRZ KR AS BADDR30 HRESET H TCK PB25 PA10 PB24 J PC5 PC7 PA8 PA9 OP0 OP1 OP2 RSTCONF OP3BADDR29 BADDR28 VDDL K VDDH PD13 PA2 PC6 PA3 L N/C PC4 PA1 PB15 M EXTAL VDDL SRESET N/C IP_A3 IP_A1 IP_A6 D26 D14 D9 IRQ1 PD3 PD8 PD15 VDDL PA0 N XTAL EXTCLK WAIT_A VSSSYN IP_A5 CLKOUT D25 D21 D15 D10 D17 IRQ7 PD6 PD9 PD12 PD14 P PORST VDDSYN VSSSYN1 DP0 DP1 D29 D24 D20 D16 D11 D23 D12 IRQ0 PD4 N/C PD11 R VDDL IP_A7 IP_A2 DP3 D31 D28 D6 D19 D5 D2 D27 D13 D0 PD5 PD10 N/C T N/C IP_A0 IP_A4 DP2 D30 D7 D22 VDDL D18 D3 D1 D4 D8 MII_TXEN PD7 N/C Figure Pinout of the PBGA Package - JEDEC Standard Freescale Semiconductor Mechanical Data and Ordering Information Table 30 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments. Table Pin Assignments - JEDEC Standard Name A[0:31] TSIZ0 REG TSIZ1 RD/WR BURST BDIP GPL_B5 TS TEA BI IRQ2 RSV IRQ4 KR RETRY SPKROUT CR IRQ3 D[0:31] DP0 IRQ3 DP1 IRQ4 DP2 IRQ5 DP3 IRQ6 BR Pin Number Type B15, A15, A14, C14, D13, E11, B14, A13, C13, B13, D12, E10, C12, Bidirectional B12, A12, D11, E9, C11, A9, A11, D10, C10, B8, A10, D9, C9, C8, Three-state 3.3V only B11, A8, B10, B9, D8 Bidirectional Three-state 3.3V only Bidirectional Three-state 3.3V only Bidirectional Three-state 3.3V only Bidirectional Three-state 3.3V only Output Bidirectional Active Pull-up 3.3V only Bidirectional Active Pull-up 3.3V only Open-drain Bidirectional Active Pull-up 3.3V only Bidirectional Three-state 3.3V only Bidirectional Three-state 3.3V only Input 3.3V only R13, T11, R10, T10, T12, R9, R7, T6, T13, M10, N10, P10, P12, Bidirectional R12, M9, N9, P9, N11, T9, R8, P8, N8, T7, P11, P7, N7, M8, R11, R6, Three-state 3.3V only P6, T5, R5 Bidirectional Three-state 3.3V only Bidirectional Three-state 3.3V only Bidirectional Three-state 3.3V only Mechanical Data and Ordering Information Table Pin Assignments - JEDEC Standard continued Pin Number G4 F3 Type Bidirectional 3.3V only Bidirectional Active Pull-up 3.3V only Bidirectional 3.3V only Input 3.3V only Input 3.3V only Input 3.3V only B2, A2, D3, C3, E6, C4 D4 A3 D6 Output Output Output Output A6, D7, C7, B7 C5 Output Output A4, B4 Output Bidirectional 3.3V only Output Input 3.3V only Input 3.3V only Open-drain Freescale Semiconductor Mechanical Data and Ordering Information Table Pin Assignments - JEDEC Standard continued Name SRESET XTAL EXTAL CLKOUT EXTCLK ALE_A CE1_A CE2_A WAIT_A IP_A0 IP_A1 IP_A2 IOIS16_A IP_A3 IP_A4 IP_A5 IP_A6 IP_A7 DSCK IWP[0:1] VFLS[0:1] OP0 OP1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR[28:29] BADDR30 REG AS PA11 RXD3 M3 N1 M1 N6 N2 H1 E5 B3 N3 T2 M6 R3 M5 T3 N5 M7 R2 H2 H3, G1 K1 K2 K3 L3, L2 J3 J2 E16 Pin Number Type Open-drain Analog Output Analog Input 1.8V only Output Input 1.8V only Output Input 3.3V only Input 3.3V only Input 3.3V only Input 3.3V only Input 3.3V only Input 3.3V only Input 3.3V only Input 3.3V only Input 3.3V only Bidirectional Three-state 3.3V only Bidirectional 3.3V only Bidirectional 3.3V only Output Bidirectional 3.3V only Bidirectional 3.3V only Output Input 3.3V only Bidirectional Optional Open-drain 5V tolerant Freescale Semiconductor Name PA10 TXD3 PA9 RXD4 PA8 TXD4 PA3 CLK5 BRGO3 TIN3 PA2 CLK6 TOUT3 PA1 CLK7 BRGO4 TIN4 PA0 CLK8 TOUT4 PB31 SPISEL PB30 SPICLK PB29 SPIMOSI PB28 SPIMISO BRGO4 PB25 SMTXD1 PB24 SMRXD1 PB15 BRGO3 Mechanical Data and Ordering Information Table Pin Assignments - JEDEC Standard continued Pin Number H15 J16 J15 K16 Type Bidirectional 5V tolerant Bidirectional Optional Open-drain 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional Optional Open-drain 5V tolerant Bidirectional Optional Open-drain 5V tolerant Bidirectional Optional Open-drain 5V tolerant Bidirectional Optional Open-drain 5V tolerant Bidirectional Optional Open-drain 5V tolerant Bidirectional Optional Open-drain 5V tolerant Bidirectional 5V tolerant Freescale Semiconductor Mechanical Data and Ordering Information Table Pin Assignments - JEDEC Standard continued Name PC15 DREQ0 PC13 RTS3 PC12 RTS4 CTS3 CTS4 SDACK1 PD15 MII_RXD3 PD14 MII_RXD2 PD13 MII_RXD1 PD12 MII_MDC PD11 RXD3 MII_TX_ER PD10 TXD3 MII_RXD0 RXD4 MII_TXD0 TXD4 MII_RX_CLK RTS3 MII_RX_ER Pin Number Type Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Freescale Semiconductor Name PD6 RTS4 MII_RX_DV PD5 MII_TXD3 PD4 MII_TXD2 PD3 MII_TXD1 TMS Mechanical Data and Ordering Information Table Pin Assignments - JEDEC Standard continued Pin Number N13 Type Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Input 5V tolerant Input 5V tolerant Input 5V tolerant Input 5V tolerant Output 5V tolerant Input Bidirectional 5V tolerant Output 5V tolerant Input PLL analog GND PLL analog GND PLL analog VDD G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, Power J10, J11, K6, K7, K8, K9, K10, K11 A7, C1, D16, G15, L4, M2, R1, M15, T8 Power F5, F6, F7, F8, F9, F10, F11, F12, G5, G12, H5, H12, J5, J12, K5, K12, L5, L6, L7, L8, L9, L10, L11, L12 Power A1, A16, B16, C15, D14, E12, L13, M4, P15, R16, T1, T16 No-connect Freescale Semiconductor Mechanical Data and Ordering Information The non-JEDEC Pinout Figure 63 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the MPC866 PowerQUICC Family User’s Manual. NOTE This figure shows the top view of the device. N/C CS1 CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7 A1 N/C C WR CS0 CE2_A GPL_A3 WE3 MII_CRS BS_A3 A22 A30 A29 A27 A13 A9 A6 A0 N/C VDDL GPL_A4 CS3 CS5 GPL_A0 WE1 BS_A2 A26 A25 A21 A17 A12 A8 D A3 N/C PC15 E BDIP BI CS2 CS6 OE WE0 BS_A1 A31 A24 A20 A15 A10 A4 N/C PB29 VDDL F BR TS TEA GPL_A5 CE_1A CS4 TSIZ1 TSIZ0 A16 A11 A5 N/C PB31 PC13 PC12 PA11 CR MII_COL BB TA G PB30 TDO TMS TRST VFLS_1 RSV BURST BG ALE_A DSCK VFLS_0 FRZ KR AS BADDR30 HRESET H PB28 TDI VDDL MDIO J TCK PB25 PA10 PB24 K PC5 PC7 PA8 PA9 OP0 OP1 OP2 RSTCONF OP3BADDR29 BADDR28 VDDL EXTAL VDDL SRESET N/C IP_A3 IP_A1 IP_A6 D26 D14 L VDDH PD13 PA2 PC6 PA3 M N/C PC4 PA1 PB15 N D9 IRQ1 PD3 PD8 PD15 VDDL PA0 P XTAL EXTCLK WAIT_A VSSSYN IP_A5 CLKOUT D25 D21 D15 D10 D17 IRQ7 PD6 PD9 PD12 PD14 R PORST VDDSYN VSSSYN1 DP0 DP1 D29 D24 D20 D16 D11 D23 D12 IRQ0 PD4 N/C PD11 VDDL IP_A7 IP_A2 DP3 D31 D28 D6 D19 D5 D2 D27 D13 D0 PD5 PD10 N/C N/C IP_A0 IP_A4 DP2 D30 D7 D22 VDDL D18 D3 D8 MII_TXEN PD7 N/C Figure Pinout of the PBGA Package - non-JEDEC Freescale Semiconductor Mechanical Data and Ordering Information Table 31 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments. Table Pin Assignments - non-JEDEC Name A[0:31] TSIZ0 REG TSIZ1 RD/WR BURST BDIP GPL_B5 TS TEA BI IRQ2 RSV IRQ4 KR RETRY SPKROUT CR IRQ3 D[0:31] DP0 IRQ3 DP1 IRQ4 DP2 IRQ5 DP3 IRQ6 Pin Number Type C16, B16, B15, D15, E14, F12, C15, B14, D14, C14, E13, F11, D13, Bidirectional C13, B13, E12, F10, D12, B10, B12, E11, D11, C9, B11, E10, D10, Three-state V only D9, C12, B9, C11, C10, E9 Bidirectional Three-state V only Bidirectional Three-state V only Bidirectional Three-state V only Bidirectional Three-state V only Output Bidirectional Active Pull-up V only Bidirectional Active Pull-up V only Open-drain Bidirectional Active Pull-up V only Bidirectional Three-state V only Bidirectional Three-state V only Input V only T14, U12, T11, U11, U13, T10, T8, U7, U14, N11, P11, R11, R13, Bidirectional T13, N10, P10, R10, P12, U10, T9, R9, P9, U8, R12, R8, P8, N9, Three-state V only T12, T7, R7, U6, T6 Bidirectional Three-state V only Bidirectional Three-state V only Bidirectional Three-state V only Mechanical Data and Ordering Information Table Pin Assignments - non-JEDEC continued Name BR BG BB FRZ IRQ6 IRQ0 IRQ1 IRQ7 M_TX_CLK CS[0:5] CS6 CS7 WE0 BS_B0 IORD WE1 BS_B1 IOWR WE2 BS_B2 PCOE WE3 BS_B3 PCWE BS_A[0:3] GPL_A0 GPL_B0 OE GPL_A1 GPL_B1 GPL_A[2:3] GPL_B[2:3] UPWAITA GPL_A4 GPL_A5 PORESET Pin Number F2 H5 G4 J5 R14 N12 P13 C3, B3, E4, D4, F7, D5 E5 B4 E7 B7, E8, D8, C8 D6 E6 B5, C5 D3 F5 R2 Type Bidirectional V only Bidirectional V only Bidirectional Active Pull-up V only Bidirectional V only Input V only Input V only Input V only Output Output Output Output Output Output Bidirectional V only Output Input V only Freescale Semiconductor Name RSTCONF HRESET SRESET XTAL EXTAL CLKOUT EXTCLK ALE_A CE1_A CE2_A WAIT_A IP_A0 IP_A1 IP_A2 IOIS16_A IP_A3 IP_A4 IP_A5 IP_A6 IP_A7 DSCK IWP[0:1] VFLS[0:1] OP0 OP1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR[28:29] BADDR30 REG Mechanical Data and Ordering Information Table Pin Assignments - non-JEDEC continued Pin Number L5 K5 N4 P2 N2 P7 P3 J2 F6 C4 P4 U3 N7 T4 Type Input V only Open-drain Open-drain Analog Output Analog Input V only Output Input V only Output Input V only Input V only Input V only Input V only N6 U4 P6 N8 T3 J3 J4, H2 Input V only Input V only Input V only Input V only Input V only Bidirectional Three-state V only Bidirectional V only Bidirectional V only Output Bidirectional V only Bidirectional V only M4, M3 K4 Output Freescale Semiconductor Mechanical Data and Ordering Information Table Pin Assignments - non-JEDEC continued Name PA11 RXD3 PA10 TXD3 RXD4 TXD4 CLK5 BRGO3 TIN3 CLK6 TOUT3 CLK7 BRGO4 TIN4 CLK8 TOUT4 PB31 SPISEL PB30 SPICLK PB29 SPIMOSI PB28 SPIMISO BRGO4 Pin Number Type Input V only Bidirectional Optional Open-drain 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant Freescale Semiconductor Name PB25 SMTXD1 PB24 SMRXD1 PB15 BRGO3 PC15 DREQ0 Mechanical Data and Ordering Information Table Pin Assignments - non-JEDEC continued Pin Number J15 M17 D17 F15 F16 K15 L16 K14 Type Bidirectional Optional Open-drain 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Freescale Semiconductor Mechanical Data and Ordering Information Table Pin Assignments - non-JEDEC continued Name RXD4 MII_TXD0 TXD4 MII_RX_CLK RTS3 MII_RX_ER RTS4 MII_RX_DV MII_TXD3 MII_TXD2 MII_TXD1 DSDI DSCK TRST DSDO MII_CRS MII_MDIO MII_TX_EN MII_COL VSSSYN VSSSYN1 VDDSYN Pin Number Type Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Input 5 V-tolerant Input 5 V-tolerant Input 5 V-tolerant Input 5 V-tolerant Output 5 V-tolerant Input Bidirectional 5 V-tolerant Output 5 V-tolerant Input PLL analog GND PLL analog GND PLL analog VDD Freescale Semiconductor Name GND VDDL VDDH Mechanical Data and Ordering Information Table Pin Assignments - non-JEDEC continued Pin Number Type H7, H8, H9, H10, H11, H12, J7, J8, J9, J10, J11, J12, K7, K8, K9, Power K10, K11, K12, L7, L8, L9, L10, L11, L12 B8, D2, E17, H16, M5, N3, T2, N16, U9 Power G6, G7, G8, G9, G10, G11, G12, G13, H6, H13, J6, J13, K6, K13, Power L6, L13, M6, M7, M8, M9, M10, M11, M12, M13 B2, B17, C17, D16, E15, F13, M14, N5, R16, T17, U2, U17 No-connect Freescale Semiconductor Mechanical Data and Ordering Information Mechanical Dimensions of the PBGA Package For more information on the printed circuit board layout of the PBGA package, including thermal via design and suggested pad layout, refer to Plastic Ball Grid Array Application Note order number AN1231/D that is available from your local Motorola sales office. Figure 64 shows the mechanical dimensions of the PBGA package. Freescale Semiconductor Mechanical Data and Ordering Information NOTES All dimensions are in millimeters. Interpret dimensions and tolerances per ASME Maximum solder ball diameter measured parallel to datum A. Datum A, the seating plane, is defined by the spherical crowns of the solder balls. Note Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC852TVRXXX. Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC852TZTXXX. Figure Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package Freescale Semiconductor Date 1/18/2005 11/2004 12/2003 7/2003 5/2003 4/2003 4/2003 2/2003 1/2003 1/2003 12/2002 11/2002 10/2002 Changes Document template update. • Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for Integer Values • Added a footnote to Spec 41 specifying that EDM = 1 • Broke the Section “Pin Assignments,” into 2 smaller sections for the JEDEC and non-JEDEC pinouts. Put 852T on the 1st page in place of Figure 62 on page 59 had overbars added on signals CR pin G2 and WAIT_A pin P4 . Changed the pinout to be JEDEC Compliant, changed timing parameters B28a through B28d, and B29d to show that TRLX can be 0 or Changed the SPI Master Timing Specs. 162 and 164 Changed the package drawing in Figure 15-63 Changed 5 Port C pins with interrupt capability to 7 Port C pins. Added the Note solder sphere composition for MPC852TVR and MPC852TCVR devices is 95.5%Sn 45%Ag 0.5%Cu to Figure 15-63 Changed Table 15-30 Pin Assignments for the PLL Pins VSSSYN1, VSSSYN, VDDSYN Added subscripts to timing diagrams for B1-B35, to specify memory controller settings for the specific edges. In Table 15-30, specified EXTCLK as V. Added fast Ethernet controller to the features Added values for 80 and 100 MHz Initial release Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK Freescale Semiconductor How to Reach Us: Home Page: email: USA/Europe or Locations Not Listed Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 800 521-6274 480-768-2130 Europe, Middle East, and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 English +46 8 52200080 English +49 89 92103 559 German +33 1 69 35 48 French Japan Freescale Semiconductor Japan Ltd. Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-0047 Japan 0120 191014 +81 3 3440 3569 Asia/Pacific Freescale Semiconductor Hong Kong Ltd. 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MPC852T Hardware Specifications

This document contains detailed information for the MPC852T about power considerations, DC/AC electrical characteristics, AC timing specifications, and pertinent electrical and physical characteristics of the MPC852T. For information about functional characteristics of the processor, refer to the MPC866 PowerQUICC Family Users Manual MPC866UM . The MPC852T contains a PowerPCTM processor core.

The MPC852T PowerQUICCTM is a 0.18-micron derivative of the MPC860 PowerQUICC family, and can operate up to 100 MHz on the MPC8xx core with a 66-MHz external bus. The MPC852T has a V core and a V I/O operation with 5-V TTL compatibility. The MPC852T integrated communications controller is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in Ethernet control applications, including CPE equipment, Ethernet routers and hubs, VoIP clients, and WiFi access points.

The MPC852T is a PowerPC architecture-based derivative of the Motorola MPC860 Quad Integrated Communications Controller PowerQUICC . The CPU on the MPC852T is the MPC8xx core, a 32-bit microprocessor that implements the PowerPC architecture, incorporating memory management units MMUs and instruction and data caches. The MPC852T is the subset of this family of devices.
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2 Features

The MPC852T is comprised of three modules that each use the 32-bit internal bus the MPC8xx core, the system integration unit SIU , and the communication processor module CPM . Figure 1 shows the MPC852T block diagram.

The following list summarizes the key MPC852T features
• Embedded MPC8xx core up to 100 MHz
• Maximum frequency operation of the external bus is 66 MHz The 50 MHz / 66 MHz core frequencies support both 1:1 and 2:1 modes. The 80 MHz / 100 MHz core frequencies support 2:1 mode only.
• Single-issue, 32-bit core compatible with the PowerPC architecture definition with 32-bit general-purpose registers GPRs The core performs branch prediction with conditional prefetch, without conditional execution. 4-Kbyte data cache and 4-Kbyte instruction cache 4-Kbyte instruction cache is two-way, set-associative with 128 sets. 4-Kbyte data cacheis two-way, set-associative with 128 sets. Cache coherency for both instruction and data caches is maintained on 128-bit 4-word cache blocks. Caches are physically addressed, implement a least recently used LRU replacement algorithm, and are lockable on a cache block basis. MMUs with 32-entry TLB, fully associative instruction, and data TLBs MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes 16 virtual address spaces, and 16 protection groups
• Up to 32-bit data bus dynamic bus sizing for 8, 16, and 32 bits
• 32 address lines
• Memory controller eight banks Contains complete dynamic RAM DRAM controller Each bank can be a chip select or RAS to support a DRAM bank Up to 30 wait states programmable per memory bank Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices DRAM controller-programmable to support most size and speed memory interfaces Four CAS lines, four WE lines, and one OE line Boot chip-select available at reset options for 8-, 16-, or 32-bit memory Variable block sizes 32 Mbytes Selectable write protection On-chip bus arbitration logic
• Fast Ethernet Controller FEC
• General-purpose timers Two 16-bit timers or one 32-bit timer Gate mode can enable or disable counting. Interrupt can be masked on reference match and event capture.

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• System integration unit SIU Bus monitor Software watchdog Periodic interrupt timer PIT Clock synthesizer Decrementer and time base Reset controller IEEE test access port JTAG
• Interrupts Seven external interrupt request IRQ lines Seven port pins with interrupt capability Eighteen internal interrupt sources Programmable priority between SCCs Programmable highest-priority request
• Communications processor module CPM RISC controller Communication-specific commands for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and RESTART TRANSMIT Supports continuous mode transmission and reception on all serial channels 8-Kbytes of dual-port RAM 8 serial DMA SDMA channels Three parallel I/O registers with open-drain capability
• Two baud rate generators Independent can be connected toany SCC3/4 or SMC1 Allows changes during operation Autobaud support option
• Two SCCs serial communication controllers Ethernet/IEEE optional on SCC3 & SCC4, supporting full 10-Mbps operation HDLC/SDLC HDLC bus implements an HDLC-based local area network LAN Universal asynchronous receiver transmitter UART Totally transparent bit streams Totally transparent frame-based with optional cyclic redundancy check CRC
• One SMC serial management channels UART
• One SPI serial peripheral interface Supports master and slave modes Supports multimaster operation on the same bus
• PCMCIA interface Master socket interface, release compliant

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Supports one independent PCMCIA socket 8-memory or I/O windows supported
• Debug interface

Eight comparators four operate on instruction address, two operate on data address, and two operate on data

Supports conditions = < > Each watchpoint can generate a break point internally.
• Normal high and normal low power modes to conserve power
• V Core and V I/O operation with 5-V TTL compatibility. Refer to Table 5 for a listing of the 5-V Tolerant pins.

Embedded MPC8xx Processor Core

Instruction
4-Kbyte

Bus Instruction Cache

Instruction MMU 32-Entry ITLB

Load/Store 4-Kbyte

Data Cache

Data MMU 32-Entry DTLB

Fast Ethernet Controller

DMAs

Unified Bus

System Interface Unit SIU

Memory Controller

Internal

External

Bus Interface Bus Interface

Unit

Unit

System Functions

PCMCIA-ATA Interface

FIFOs
10/100 Base-T Media Access Control

Parallel I/O
2 Baud Rate Generators
Mechanical Data and Ordering Information
16 Mechanical Data and Ordering Information

Table 29 identifies the packages and operating frequencies orderable for the MPC852T. Table MPC852T Package/Frequency Orderable

Package Type Plastic ball grid array VR and ZT suffix

Plastic ball grid array CVR suffix

Temperature Tj 0°C to 95°C
40°C to 100°C

Frequency MHz 50 66 80 100 66

Order Number

MPC852TVR50 MPC852TZT50

MPC852TVR66 MPC852TZT66

MPC852TVR80 MPC852TZT80

MPC852TVR100 MPC852TZT100

Pin Assignments

The following sections give the pinout and pin listing for the JEDEC Compliant and the non-JEDEC versions of the 16 x 16 PBGA package.

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Mechanical Data and Ordering Information

The JEDEC Compliant Pinout

Figure 62 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the MPC866 PowerQUICC Family User’s Manual.

NOTE This is the top view of the device.

A N/C CS1 CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7 A2 A1 N/C

B WR CS0 CE2_A GPL_A3 WE3 MII_CRS BS_A3 A22 A30 A29 A27 A13 A9 A6 A0 N/C

VDDL GPL_A4 CS3 CS5 GPL_A0 WE1 BS_A2 A26 A25 A21 A17 A12 A8

C A3 N/C PC15

D BDIP BI CS2 CS6 OE WE0 BS_A1 A31 A24 A20 A15 A10 A4 N/C PB29 VDDL

E BR TS TEA GPL_A5 CE_1A CS4 TSIZ1 TSIZ0 A16 A11 A5 N/C PB31 PC13 PC12 PA11

CR MII_COL BB TA

F PB30 TDO TMS TRST

VFLS_1 RSV BURST BG

G PB28 TDI VDDL MDIO

ALE_A DSCK VFLS_0 FRZ KR AS BADDR30 HRESET

H TCK PB25 PA10 PB24

J PC5 PC7 PA8 PA9

OP0 OP1 OP2 RSTCONF OP3BADDR29 BADDR28 VDDL

K VDDH PD13 PA2 PC6 PA3

L N/C PC4 PA1 PB15

M EXTAL VDDL SRESET N/C IP_A3 IP_A1 IP_A6 D26 D14 D9 IRQ1 PD3 PD8 PD15 VDDL PA0

N XTAL EXTCLK WAIT_A VSSSYN IP_A5 CLKOUT D25 D21 D15 D10 D17 IRQ7 PD6 PD9 PD12 PD14

P PORST VDDSYN VSSSYN1 DP0 DP1 D29 D24 D20 D16 D11 D23 D12 IRQ0 PD4 N/C PD11

R VDDL IP_A7 IP_A2 DP3 D31 D28 D6 D19 D5 D2 D27 D13 D0 PD5 PD10 N/C

T N/C IP_A0 IP_A4 DP2 D30 D7 D22 VDDL D18 D3 D1 D4 D8 MII_TXEN PD7 N/C

Figure Pinout of the PBGA Package - JEDEC Standard

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Mechanical Data and Ordering Information

Table 30 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments. Table Pin Assignments - JEDEC Standard

Name A[0:31]

TSIZ0 REG TSIZ1

RD/WR

BURST

BDIP GPL_B5 TS

TEA BI

IRQ2 RSV IRQ4 KR RETRY SPKROUT CR IRQ3 D[0:31]

DP0 IRQ3 DP1 IRQ4 DP2 IRQ5 DP3 IRQ6 BR

Pin Number

Type

B15, A15, A14, C14, D13, E11, B14, A13, C13, B13, D12, E10, C12, Bidirectional B12, A12, D11, E9, C11, A9, A11, D10, C10, B8, A10, D9, C9, C8, Three-state 3.3V only B11, A8, B10, B9, D8

Bidirectional

Three-state 3.3V only

Bidirectional

Three-state 3.3V only

Bidirectional

Three-state 3.3V only

Bidirectional

Three-state 3.3V only

Output

Bidirectional

Active Pull-up 3.3V only

Bidirectional

Active Pull-up 3.3V only

Open-drain

Bidirectional

Active Pull-up 3.3V only

Bidirectional

Three-state 3.3V only

Bidirectional

Three-state 3.3V only

Input 3.3V only

R13, T11, R10, T10, T12, R9, R7, T6, T13, M10, N10, P10, P12, Bidirectional R12, M9, N9, P9, N11, T9, R8, P8, N8, T7, P11, P7, N7, M8, R11, R6, Three-state 3.3V only P6, T5, R5

Bidirectional

Three-state 3.3V only

Bidirectional

Three-state 3.3V only

Bidirectional

Three-state 3.3V only
Mechanical Data and Ordering Information

Table Pin Assignments - JEDEC Standard continued

Pin Number G4 F3

Type

Bidirectional 3.3V only Bidirectional Active Pull-up 3.3V only Bidirectional 3.3V only

Input 3.3V only

Input 3.3V only

Input 3.3V only

B2, A2, D3, C3, E6, C4 D4 A3 D6

Output

Output

Output

Output

A6, D7, C7, B7 C5

Output

Output

A4, B4

Output

Bidirectional 3.3V only

Output

Input 3.3V only

Input 3.3V only

Open-drain

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Mechanical Data and Ordering Information

Table Pin Assignments - JEDEC Standard continued

Name

SRESET XTAL EXTAL CLKOUT EXTCLK ALE_A CE1_A CE2_A WAIT_A IP_A0 IP_A1 IP_A2 IOIS16_A IP_A3 IP_A4 IP_A5 IP_A6 IP_A7 DSCK

IWP[0:1] VFLS[0:1] OP0 OP1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR[28:29] BADDR30 REG AS PA11 RXD3

M3 N1 M1 N6 N2 H1 E5 B3 N3 T2 M6 R3

M5 T3 N5 M7 R2 H2

H3, G1

K1 K2 K3

L3, L2 J3

J2 E16

Pin Number

Type Open-drain Analog Output Analog Input 1.8V only Output Input 1.8V only Output Input 3.3V only Input 3.3V only Input 3.3V only Input 3.3V only

Input 3.3V only Input 3.3V only Input 3.3V only Input 3.3V only Input 3.3V only Bidirectional Three-state 3.3V only Bidirectional 3.3V only

Bidirectional 3.3V only Output Bidirectional 3.3V only

Bidirectional 3.3V only

Output

Input 3.3V only Bidirectional Optional Open-drain 5V tolerant

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Name

PA10 TXD3 PA9 RXD4

PA8 TXD4 PA3 CLK5 BRGO3 TIN3 PA2 CLK6 TOUT3 PA1 CLK7 BRGO4 TIN4 PA0 CLK8 TOUT4 PB31 SPISEL

PB30 SPICLK

PB29 SPIMOSI

PB28 SPIMISO BRGO4 PB25 SMTXD1

PB24 SMRXD1

PB15 BRGO3
Mechanical Data and Ordering Information

Table Pin Assignments - JEDEC Standard continued

Pin Number H15 J16

J15 K16

Type

Bidirectional 5V tolerant

Bidirectional Optional Open-drain 5V tolerant

Bidirectional 5V tolerant

Bidirectional 5V tolerant

Bidirectional
5V tolerant

Bidirectional
5V tolerant

Bidirectional
5V tolerant

Bidirectional

Optional Open-drain
5V tolerant

Bidirectional

Optional Open-drain
5V tolerant

Bidirectional

Optional Open-drain
5V tolerant

Bidirectional

Optional Open-drain
5V tolerant

Bidirectional

Optional Open-drain
5V tolerant

Bidirectional

Optional Open-drain
5V tolerant

Bidirectional
5V tolerant

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Mechanical Data and Ordering Information

Table Pin Assignments - JEDEC Standard continued

Name

PC15

DREQ0

PC13

RTS3

PC12

RTS4

CTS3

CTS4

SDACK1

PD15

MII_RXD3

PD14

MII_RXD2

PD13

MII_RXD1

PD12

MII_MDC

PD11

RXD3

MII_TX_ER

PD10

TXD3

MII_RXD0

RXD4

MII_TXD0

TXD4

MII_RX_CLK

RTS3

MII_RX_ER

Pin Number

Type Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant

Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant Bidirectional 5V tolerant

Bidirectional 5V tolerant

Bidirectional 5V tolerant

Bidirectional 5V tolerant

Bidirectional 5V tolerant

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Name PD6 RTS4 MII_RX_DV PD5 MII_TXD3 PD4 MII_TXD2 PD3 MII_TXD1 TMS
Mechanical Data and Ordering Information

Table Pin Assignments - JEDEC Standard continued

Pin Number N13

Type

Bidirectional 5V tolerant

Bidirectional
5V tolerant

Bidirectional
5V tolerant

Bidirectional
5V tolerant

Input
5V tolerant

Input
5V tolerant

Input
5V tolerant

Input
5V tolerant

Output
5V tolerant

Input

Bidirectional
5V tolerant

Output
5V tolerant

Input

PLL analog GND

PLL analog GND

PLL analog VDD

G6, G7, G8, G9, G10, G11, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, Power J10, J11, K6, K7, K8, K9, K10, K11

A7, C1, D16, G15, L4, M2, R1, M15, T8

Power

F5, F6, F7, F8, F9, F10, F11, F12, G5, G12, H5, H12, J5, J12, K5, K12, L5, L6, L7, L8, L9, L10, L11, L12

Power

A1, A16, B16, C15, D14, E12, L13, M4, P15, R16, T1, T16

No-connect

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Mechanical Data and Ordering Information

The non-JEDEC Pinout

Figure 63 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the MPC866 PowerQUICC Family User’s Manual.

NOTE This figure shows the top view of the device.

N/C CS1 CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7

A1 N/C

C WR CS0 CE2_A GPL_A3 WE3 MII_CRS BS_A3 A22 A30 A29 A27 A13 A9 A6 A0 N/C

VDDL GPL_A4 CS3 CS5 GPL_A0 WE1 BS_A2 A26 A25 A21 A17 A12 A8

D A3 N/C PC15

E BDIP BI CS2 CS6 OE WE0 BS_A1 A31 A24 A20 A15 A10 A4 N/C PB29 VDDL

F BR TS TEA GPL_A5 CE_1A CS4 TSIZ1 TSIZ0 A16 A11 A5 N/C PB31 PC13 PC12 PA11

CR MII_COL BB TA

G PB30 TDO TMS TRST

VFLS_1 RSV BURST BG ALE_A DSCK VFLS_0 FRZ

KR AS BADDR30 HRESET

H PB28 TDI VDDL MDIO

J TCK PB25 PA10 PB24

K PC5 PC7 PA8 PA9

OP0 OP1 OP2 RSTCONF OP3BADDR29 BADDR28 VDDL EXTAL VDDL SRESET N/C IP_A3 IP_A1 IP_A6 D26 D14

L VDDH PD13 PA2 PC6 PA3

M N/C PC4 PA1 PB15

N D9 IRQ1 PD3 PD8 PD15 VDDL PA0

P XTAL EXTCLK WAIT_A VSSSYN IP_A5 CLKOUT D25 D21 D15 D10 D17 IRQ7 PD6 PD9 PD12 PD14

R PORST VDDSYN VSSSYN1 DP0 DP1 D29 D24 D20 D16 D11 D23 D12 IRQ0 PD4 N/C PD11

VDDL IP_A7 IP_A2 DP3 D31 D28 D6 D19 D5

D2 D27 D13 D0 PD5 PD10 N/C

N/C IP_A0 IP_A4 DP2 D30 D7 D22 VDDL D18 D3

D8 MII_TXEN PD7 N/C

Figure Pinout of the PBGA Package - non-JEDEC

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Mechanical Data and Ordering Information

Table 31 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments. Table Pin Assignments - non-JEDEC

Name A[0:31]

TSIZ0 REG TSIZ1

RD/WR

BURST

BDIP GPL_B5 TS

TEA BI

IRQ2 RSV IRQ4 KR RETRY SPKROUT CR IRQ3 D[0:31]

DP0 IRQ3 DP1 IRQ4 DP2 IRQ5 DP3 IRQ6

Pin Number

Type

C16, B16, B15, D15, E14, F12, C15, B14, D14, C14, E13, F11, D13, Bidirectional C13, B13, E12, F10, D12, B10, B12, E11, D11, C9, B11, E10, D10, Three-state V only D9, C12, B9, C11, C10, E9

Bidirectional

Three-state V only

Bidirectional

Three-state V only

Bidirectional

Three-state V only

Bidirectional

Three-state V only

Output

Bidirectional

Active Pull-up V only

Bidirectional

Active Pull-up V only

Open-drain

Bidirectional

Active Pull-up V only

Bidirectional

Three-state V only

Bidirectional

Three-state V only

Input V only

T14, U12, T11, U11, U13, T10, T8, U7, U14, N11, P11, R11, R13, Bidirectional T13, N10, P10, R10, P12, U10, T9, R9, P9, U8, R12, R8, P8, N9, Three-state V only T12, T7, R7, U6, T6

Bidirectional

Three-state V only

Bidirectional

Three-state V only

Bidirectional

Three-state V only
Mechanical Data and Ordering Information

Table Pin Assignments - non-JEDEC continued

Name

BR BG BB

FRZ IRQ6 IRQ0 IRQ1 IRQ7 M_TX_CLK CS[0:5] CS6 CS7 WE0 BS_B0 IORD WE1 BS_B1 IOWR WE2 BS_B2 PCOE WE3 BS_B3 PCWE BS_A[0:3] GPL_A0 GPL_B0 OE GPL_A1 GPL_B1 GPL_A[2:3] GPL_B[2:3] UPWAITA GPL_A4 GPL_A5 PORESET

Pin Number F2 H5 G4 J5 R14 N12 P13 C3, B3, E4, D4, F7, D5 E5 B4 E7

B7, E8, D8, C8 D6 E6

B5, C5

D3 F5 R2

Type Bidirectional V only Bidirectional V only Bidirectional Active Pull-up V only Bidirectional V only Input V only Input V only Input V only Output

Output

Output

Output

Output

Output

Bidirectional V only Output Input V only

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Name

RSTCONF HRESET SRESET XTAL EXTAL CLKOUT EXTCLK ALE_A CE1_A CE2_A WAIT_A IP_A0 IP_A1 IP_A2 IOIS16_A IP_A3 IP_A4 IP_A5 IP_A6 IP_A7 DSCK

IWP[0:1] VFLS[0:1] OP0 OP1 OP2 MODCK1 STS OP3 MODCK2 DSDO BADDR[28:29] BADDR30 REG
Mechanical Data and Ordering Information

Table Pin Assignments - non-JEDEC continued

Pin Number L5 K5 N4 P2 N2 P7 P3 J2 F6 C4 P4 U3 N7 T4

Type Input V only Open-drain Open-drain Analog Output Analog Input V only Output Input V only Output Input V only Input V only Input V only Input V only

N6 U4 P6 N8 T3 J3

J4, H2

Input V only Input V only Input V only Input V only Input V only Bidirectional Three-state V only Bidirectional V only

Bidirectional V only

Output

Bidirectional V only

Bidirectional V only

M4, M3 K4

Output

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Mechanical Data and Ordering Information

Table Pin Assignments - non-JEDEC continued

Name

PA11

RXD3

PA10

TXD3

RXD4

TXD4

CLK5

BRGO3

TIN3

CLK6

TOUT3

CLK7

BRGO4

TIN4

CLK8

TOUT4

PB31

SPISEL

PB30

SPICLK

PB29

SPIMOSI

PB28

SPIMISO

BRGO4

Pin Number

Type

Input V only Bidirectional Optional Open-drain 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant Bidirectional 5 V-tolerant

Bidirectional 5 V-tolerant

Bidirectional 5 V-tolerant

Bidirectional 5 V-tolerant

Bidirectional Optional Open-drain 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant Bidirectional Optional Open-drain 5 V-tolerant

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Name

PB25 SMTXD1

PB24 SMRXD1

PB15 BRGO3

PC15 DREQ0
Mechanical Data and Ordering Information

Table Pin Assignments - non-JEDEC continued

Pin Number J15

M17 D17 F15 F16 K15 L16 K14

Type

Bidirectional Optional Open-drain 5 V-tolerant

Bidirectional Optional Open-drain 5 V-tolerant

Bidirectional 5 V-tolerant

Bidirectional 5 V-tolerant

Bidirectional 5 V-tolerant

Bidirectional 5 V-tolerant

Bidirectional 5 V-tolerant

Bidirectional 5 V-tolerant

Bidirectional 5 V-tolerant

Bidirectional
5 V-tolerant

Bidirectional
5 V-tolerant

Bidirectional
5 V-tolerant

Bidirectional
5 V-tolerant

Bidirectional
5 V-tolerant

Bidirectional
5 V-tolerant

Bidirectional
5 V-tolerant

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Mechanical Data and Ordering Information

Table Pin Assignments - non-JEDEC continued

Name

RXD4

MII_TXD0

TXD4

MII_RX_CLK

RTS3

MII_RX_ER

RTS4

MII_RX_DV

MII_TXD3

MII_TXD2

MII_TXD1

DSDI

DSCK

TRST

DSDO

MII_CRS

MII_MDIO

MII_TX_EN

MII_COL

VSSSYN

VSSSYN1

VDDSYN

Pin Number

Type

Bidirectional 5 V-tolerant

Bidirectional 5 V-tolerant

Bidirectional 5 V-tolerant

Bidirectional 5 V-tolerant

Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Bidirectional 5 V-tolerant Input 5 V-tolerant Input 5 V-tolerant Input 5 V-tolerant Input 5 V-tolerant Output 5 V-tolerant Input Bidirectional 5 V-tolerant Output 5 V-tolerant Input PLL analog GND PLL analog GND PLL analog VDD

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Name GND

VDDL VDDH
Mechanical Data and Ordering Information

Table Pin Assignments - non-JEDEC continued

Pin Number

Type

H7, H8, H9, H10, H11, H12, J7, J8, J9, J10, J11, J12, K7, K8, K9, Power K10, K11, K12, L7, L8, L9, L10, L11, L12

B8, D2, E17, H16, M5, N3, T2, N16, U9

Power

G6, G7, G8, G9, G10, G11, G12, G13, H6, H13, J6, J13, K6, K13, Power L6, L13, M6, M7, M8, M9, M10, M11, M12, M13

B2, B17, C17, D16, E15, F13, M14, N5, R16, T17, U2, U17

No-connect

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Mechanical Data and Ordering Information

Mechanical Dimensions of the PBGA Package

For more information on the printed circuit board layout of the PBGA package, including thermal via design and suggested pad layout, refer to Plastic Ball Grid Array Application Note order number AN1231/D that is available from your local Motorola sales office. Figure 64 shows the mechanical dimensions of the PBGA package.

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Mechanical Data and Ordering Information

NOTES All dimensions are in millimeters. Interpret dimensions and tolerances per ASME Maximum solder ball diameter measured parallel to datum A. Datum A, the seating plane, is defined by the spherical crowns of the solder balls.

Note Solder sphere composition is 95.5%Sn 45%Ag 0.5%Cu for MPC852TVRXXX.

Solder sphere composition is 62%Sn 36%Pb 2%Ag for MPC852TZTXXX.

Figure Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package

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Date 1/18/2005 11/2004
12/2003
7/2003
5/2003 4/2003 4/2003
2/2003 1/2003 1/2003 12/2002 11/2002 10/2002

Changes

Document template update.
• Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for Integer Values
• Added a footnote to Spec 41 specifying that EDM = 1
• Broke the Section “Pin Assignments,” into 2 smaller sections
for the JEDEC and non-JEDEC pinouts.

Put 852T on the 1st page in place of Figure 62 on page 59 had overbars added on signals CR pin G2 and WAIT_A pin P4 .

Changed the pinout to be JEDEC Compliant, changed timing parameters B28a through B28d, and B29d to show that TRLX can be 0 or

Changed the SPI Master Timing Specs. 162 and 164

Changed the package drawing in Figure 15-63

Changed 5 Port C pins with interrupt capability to 7 Port C pins. Added the Note solder sphere composition for MPC852TVR and MPC852TCVR devices is 95.5%Sn 45%Ag 0.5%Cu to Figure 15-63

Changed Table 15-30 Pin Assignments for the PLL Pins VSSSYN1, VSSSYN, VDDSYN Added subscripts to timing diagrams for B1-B35, to specify memory controller settings for the specific edges.

In Table 15-30, specified EXTCLK as V.

Added fast Ethernet controller to the features

Added values for 80 and 100 MHz

Initial release

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Datasheet ID: MPC852TVR66 635551