MC9S12T64CPKE16
MC9S12T64CPKE16 Datasheet
MC9S12T64
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MC9S12T64CPKE16 |
MC9S12T64CPKE16 (pdf) |
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MC9S12T64MPKE16 |
MC9S12T64MPKE16 |
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| Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. DOCUMENT NUMBER 9S12T64AF16V1/D MC9S12T64 For More Information On This Product, Go to: Freescale Semiconductor, Inc. Contents - Initial Release. Jan-28-2003 - Added document number information. Feb-13-2003 - a diagram of FBDM data transfer in SPI mode in FBDM section page - Corrected order number in ordering information page Feb-28-2003 Freescale Semiconductor, Inc... MC9S12T64Revision For More Information On This Product, Go to: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... List of Sections List of Sections 3 Table of Contents 5 List of Figures 11 List of Tables 15 General Description 19 Central Processing Unit CPU 25 Pinout and Signal Description 59 System Configuration 79 Registers 85 Operating Modes 105 Module Mapping Control MMC 121 Multiplexed External Bus Interface MEBI 141 Resets and Interrupts. 169 Voltage Regulator VREG 181 Low-Voltage Detector LVD 185 Flash EEPROM 64K 193 CALRAM 2K 235 Port Integration Module PIM 249 Clocks and Reset Generator CRG 271 Pulse Width Modulator PWM8B8C 327 Enhanced Capture Timer ECT 371 Serial Communications Interface SCI . 419 Serial Peripheral Interface SPI 457 Analog to Digital Converter ATD 487 Fast Background Debug Module FBDM 517 Breakpoint BKP 547 Electrical Characteristics 561 591 Glossary 595 Literature Updates 605 List of Sections For More Information On This Product, Go to: MC9S12T64Revision List of Sections Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MC9S12T64Revision List of Sections For More Information On This Product, Go to: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table of Contents List of Sections Table of Contents List of Figures List of Tables General Description Central Processing Unit CPU Pinout and Signal Description System Configuration Registers Operating Modes Contents 19 Introduction 19 Features 20 MC9S12T64 Block Diagram 23 Ordering Information 24 Contents 25 Introduction 25 Programming Model 26 Data Format Summary 34 Addressing Modes 35 Instruction Set Overview 36 Contents 59 MC9S12T64 Pin Assignments in 80-pin LQFP 59 Power Supply Pins 62 Signal Descriptions 65 Port Signals 74 Contents 79 Introduction 79 Modules Variabilities 79 MCU Variabilities 80 System Clock Description 81 Contents 85 Register Block 85 General Purpose Registers 103 Contents 105 Introduction 105 Operating Modes 105 Background Debug Mode 116 Table of Contents For More Information On This Product, Go to: MC9S12T64Revision Table of Contents Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Module Mapping Control MMC Multiplexed External Bus Interface MEBI Resets and Interrupts Voltage Regulator VREG Low-Voltage Detector LVD Secured Mode of Operation 117 Contents 121 Overview 121 Features 121 Block Diagram 122 Register Map 123 Register Descriptions 125 Functional Description 133 Memory Maps 138 Contents 141 Overview 141 Modes of Operation 141 External Pin Descriptions 142 Register Map 145 Register Descriptions 146 Functional Description 161 Low-Power Options 167 Contents 169 Introduction 169 Register Map 170 Exception Priority 171 Maskable interrupts 171 Latching of Interrupts 172 Register Descriptions 175 Resets 177 Effects of Reset 178 Contents 181 Overview 181 Features 181 Modes of Operation 181 Block Diagram 183 Functional Description 184 Reset Initialization 184 Contents 185 Glossary 185 Overview 185 Features 186 Modes of Operation 186 Block Diagram 187 Register Map 188 Register Descriptions 189 Functional Description 191 Interrupts 192 MC9S12T64Revision Table of Contents For More Information On This Product, Go to: Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... Flash EEPROM 64K CALRAM 2K Port Integration Module PIM Clocks and Reset Generator CRG Contents Overview Glossary Features Modes of Operation Block Diagram External Pin Descriptions Module Memory Map Register Descriptions Functional Description Low Power Options Background Debug Mode Flash Security Reset Initialization Interrupts Contents Glossary Overview Features Modes of Operations Block Diagram External Pin Descriptions Module Memory Map Register Descriptions Functional Description Reset Initialization Contents Overview Block Diagram External Pin Descriptions Register Map Register Descriptions Functional Description Low Power Options Reset Initialization Contents Overview Features Modes of Operation Block Diagram External Pin Descriptions Register Map Register Descriptions Functional Description Operation Modes Table of Contents For More Information On This Product, Go to: MC9S12T64Revision Table of Contents MC9S12T64 Device Ordering Information 24 MC9S12T64 Development Tools Ordering Information 24 Addressing Mode Summary 35 Instruction Set Summary 36 Register and Memory 51 Source Form Notation 53 Operation Notation 54 Address Mode Notation 54 Machine Code Notation 55 Access Detail Notation 55 Condition Code State Notation 58 MC9S12T64 Power and Ground Connection Summary 64 MC9S12T64 Signal Description Summary 70 MC9S12T64 Port A, B, E, K, T, S, P Description Summary................................ 77 Port A, B, E, K, AD Pull-Up, Pull-Down and Reduced Drive Summary 78 MMC Module Variable I/O Signals 79 Assigned Part ID Numbers 80 Module Availability in WAIT and RUN Modes 83 MC9S12T64 Register Map 86 Mode 106 MODC, MODB, MODA Write 115 Security Bits 118 EXSTR Stretch Bit Definition 128 State of ROMON bit after reset 129 Program space page index in special 133 Mapping Precedence 134 Access Type in Expanded Modes 135 64K Byte Physical Flash/ROM Allocated 135 External System Pins Associated With 142 Access Type vs. Bus Control Pins 162 IPIPE[1:0] Decoding when E Clock is High 165 IPIPE[1:0] Decoding when E Clock is Low 165 Interrupt Vector 172 LVDF Flag Indication 190 Flash Memory Mapping in Normal 198 Flash Memory Mapping in Special Modes 200 Flash Protection/Security 202 Memory Map Summary In Normal 203 Example FCLKDIV settings 207 List of Tables For More Information On This Product, Go to: MC9S12T64Revision List of Tables Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Security States 208 Register Bank Selects 210 Loading of the Protection Register from Flash 211 Higher Address Range 212 Lower Address Range Protection 213 Valid User Mode Commands 216 Flash Interrupt Sources 232 Example CALRAM Mapping 242 Port Reset State and Priority Summary 252 Pin Configuration Summary 255 Clock Selection Based on XCLKS at reset 278 RTI Frequency Divide Rates 289 COP Watchdog Rates 292 MCU configuration during Wait Mode 306 Outcome of Clock Loss in Wait Mode 309 Outcome of Clock Loss in Pseudo-Stop Mode 314 Reset Summary 318 Reset Vector 319 Relation between PORLVDRF and 323 CRG Interrupt 324 Clock B Prescaler Selects 341 Clock A Prescaler Selects 341 PWM Timer Counter 360 16-bit Concatenation Mode 366 PWM Boundary Cases 367 Compare Result Output Action 385 Edge Detector Circuit 386 Prescaler Selection 388 Pin Action 392 Clock Selection 392 Modulus Counter Prescaler 397 Delay Counter Select 400 ECT Interrupts 416 Loop 426 Example of 8-bit Data Formats 436 Example of 9-Bit Data Formats 436 Baud Rates Example Bus Clock = MHz 437 Start Bit 444 Data Bit Recovery 445 Stop Bit Recovery 445 SCI Interrupt 454 SS Input / Output Selection 463 Bidirectional Pin Configurations 465 SPI Baud Rate Selection 16 MHz Bus 466 Normal Mode and Bidirectional Mode 481 SPI Interrupt Signals 485 External Trigger Configurations 495 MC9S12T64Revision List of Tables For More Information On This Product, Go to: Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. List of Tables Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 Table 109 Table 110 Table 111 Table 112 Table 113 Table 114 Table 115 Table 116 Table 117 Table 118 Table 119 Table 120 Table 121 Conversion Sequence Length Coding. ATD Behavior in Freeze Mode Sample Time Clock Prescaler Result Data Formats Available. Left Justified, Signed and Unsigned ATD Output Analog Input Channel Select Special Channel Select Coding External Trigger Control ATD module Interrupt Vectors Target Clock Selection Summary Hardware Firmware Commands SPI Mode Timing Tag Pin Breakpoint Mask Bits for First Breakpoint Mask Bits for Second Address Dual Address Mode Breakpoint Mask Bits for Data Breakpoints Full Breakpoint Mode .................556 Absolute Maximum Ratings Operating Conditions Thermal Package 5V I/O Supply Current Characteristics ATD Operating Characteristics ATD Electrical Characteristics ATD Conversion NVM Timing Characteristics NVM Reliability Voltage Regulator Recommended Load Startup Characteristics Oscillator Characteristics PLL SPI Master Mode Timing Characteristics SPI Slave Mode Timing Characteristics Expanded Bus Timing Characteristics 16MHz List of Tables For More Information On This Product, Go to: MC9S12T64Revision List of Tables Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MC9S12T64Revision List of Tables For More Information On This Product, Go to: Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Contents Introduction 19 Features 20 MC9S12T64 Block Diagram 23 Ordering Information 24 Introduction The MC9S12T64 microcontroller unit MCU is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit HCS12 CPU , 64K bytes of Flash EEPROM, 2K bytes of RAM, 2K bytes of CALRAM Calibration RAM , two asynchronous serial communications interfaces SCI , one serial peripheral interface SPI , an 8 channel IC/OC enhanced capture timer, an 8-channel 10-bit analog-to-digital converter ADC , an 8-channel pulse-width modulator PWM , 25 discrete digital I/O channels Port A, Port B, Port E and Port K . System resource mapping, clock generation, interrupt control and bus interfacing are managed by the System Integration Module SIM . The MC9S12T64 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. For More Information On This Product, Go to: MC9S12T64Revision Freescale Semiconductor, Inc. General Description Freescale Semiconductor, Inc... • HCS12 Core 16-bit HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer’s model identical to M68HC11 iii. 20-bit ALU iv. Instruction queue v. Enhanced indexed addressing MEBI Multiplexed External Bus Interface 1 MMC Module Mapping Control INT Interrupt control BKP Breakpoints FBDM Fast Background Debug Mode i. Synchronous Serial Peripheral Interface SPI mode to allow fast read and write of internal memory contents. ii. 4M bit per second in SPI mode at 16MHz bus iii. Single Wire Interface • CRG low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor • LVD Low Voltage Detector Low Voltage Detector to pull reset when the VDDR Supply Voltage falls to LVD trip voltage. • 64K byte Flash EEPROM 2 Two 32K byte Flash EEPROM blocks independently programmable and erasable Internal Flash EEPROM must be disabled to connect external memory devices with the external bus. Whole 64K bytes of Flash EEPROM can not be used at a time, since 1K byte register block and 2K byte RAM array are always overlapped with Flash EEPROM. MC9S12T64Revision For More Information On This Product, Go to: Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. General Description Features Programmable during calibration • 2K byte RAM Single cycle misaligned 16-bit access • 2K byte CALRAM Calibration RAM 2K byte calibration block over Flash EEPROM Access cycle compatible to Flash EEPROM • 8 channel Analog-to-Digital Converters 10-bit resolution External conversion trigger • Enhanced Capture Timer 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels Two 8-bit or one 16-bit pulse accumulators • 8 PWM channels Programmable period and duty cycle 8-bit 8-channel or 16-bit 4-channel Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs • Serial interfaces Two asynchronous Serial Communications Interfaces SCI One synchronous Serial Peripheral Interface SPI • Operating Condition 32 MHz CPU equivalent to 16MHz bus operation For More Information On This Product, Go to: MC9S12T64Revision Freescale Semiconductor, Inc. General Description to 2.75V Digital Supply Voltage generated using an internal voltage regulator 4.75V to 5.25V Analog and I/O Supply Voltage 80-Pin LQFP • Technology micron CMOS Freescale Semiconductor, Inc... MC9S12T64Revision For More Information On This Product, Go to: Freescale Semiconductor, Inc. General Description MC9S12T64 Block Diagram Freescale Semiconductor, Inc... Ordering Information Package 80-Pin LQFP Table 1 MC9S12T64 Device Ordering Information Temperature Range Designator to +85 to +105 to +125 Voltage Frequency Order Number MC9S12T64CPK16 Bus 16MHz CPU 32MHz MC9S12T64VPK16 MC9S12T64MPK16 Table 2 MC9S12T64 Development Tools Ordering Information Details Order Number Contact local sales for this information. Freescale Semiconductor, Inc... MC9S12T64Revision For More Information On This Product, Go to: Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit CPU Contents Introduction 25 Programming Model 26 Data Format Summary 34 Addressing Modes 35 Instruction Set Overview 36 Introduction The HCS12 CPU is a high-speed, 16-bit processing unit. It has full 16-bit data paths and wider internal registers up to 20 bits for high-speed extended math instructions. The instruction set is a proper superset of the M68HC11instruction set. The HCS12 CPU allows instructions with odd byte counts, including many single-byte instructions. This provides efficient use of ROM space. An instruction pipe buffers program information so the CPU always has immediate access to at least three bytes of machine code at the start of every instruction. The HCS12 CPU also offers an extensive set of indexed addressing capabilities. Central Processing Unit CPU For More Information On This Product, Go to: MC9S12T64Revision Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit CPU Programming Model The Core CPU12 programming model, shown in Figure 2, is the same as that of the 68HC12 and 68HC11. The register set and data types used in the model are covered in the subsections that follow. 0 8-BIT ACCUMULATORS A AND B 0 16-BIT DOUBLE ACCUMULATOR D A B 0 INDEX REGISTER X 0 INDEX REGISTER Y 0 STACK POINTER 0 PROGRAM COUNTER S X H I N Z V C CONDITION CODE REGISTER CARRY OVERFLOW ZERO NEGATIVE IRQ INTERRUPT MASK DISABLE HALF-CARRY FOR BCD ARITHMETIC XIRQ INTERRUPT MASK DISABLE STOP DISABLE IGNORE STOP INSTRUCTION Figure 2 Programming Model Accumulators General-purpose 8-bit accumulators A and B hold operands and results of operations. Some instructions use the combined 8-bit accumulators, A:B, as a 16-bit double accumulator, D, with the most significant byte in A. MC9S12T64Revision Central Processing Unit CPU For More Information On This Product, Go to: Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit CPU Programming Model Read: Write: Reset 0 Figure 3 Accumulator A |
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