MC88LV926DWR2

MC88LV926DWR2 Datasheet

Order this document by MC88LV926/D

Part	Datasheet
MC88LV926DWR2	MC88LV926DWR2 (pdf)

PDF Datasheet Preview
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC88LV926/D Low Skew CMOS PLL 68060 Clock Driver MC88LV926 The MC88LV926 Clock Driver utilizes loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT LOCK pins provide a processor reset function designed specifically for the MC68/EC/LC030/040/060 microprocessor family. To support the 68060 processor, the 88LV926 operates from a 3.3V as well as a 5.0V supply. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88LV926 to multiply a low frequency input clock and distribute it locally at a higher 2X system frequency. LOW SKEW CMOS PLL 68060 CLOCK DRIVER • 2X_Q Output Meets All Requirements of the 50 and 66MHz 68060 Microprocessor PCLK Input Specifications • Low Voltage 3.3V VCC • Three Outputs With Skew <500ps • CLKEN Output for Half Speed Bus Applications • The Phase Variation From Between SYNC and the ‘Q’ Outputs Is Less Than 600ps Derived From the TPD Specification, Which Defines the Skew DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D • SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4 • All Outputs Have ±36mA Drive Equal High and Low CMOS Levels • Can Drive Either CMOS or TTL Inputs. All Inputs Are Compatible with VCC = 3.3V • Test Mode Pin PLL_EN Provided for Low Frequency Testing Three ‘Q’ outputs are provided with less than 500ps skew between their rising edges. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output is ideal for 68060 systems which require a 2X processor clock input, and it meets the tight duty cycle spec of the 50 and 66MHz The QCLKEN output is designed to drive the CLKEN input of the 68060 when the bus logic runs at half of the microprocessor clock rate. The QCLKEN output is skewed relative to the 2X_Q output to ensure that CLKEN setup and hold times of the 68060 are satisfied. A Q/2 frequency is fed back internally, providing a fixed 2X multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally no external feedback pin is provided the input/output frequency relationships are fixed. The Q3 output provides an inverted clock output to allow flexibility in the clock tree design. In normal operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88LV926 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The RST_OUT LOCK pin doubles as a indicator. When the RST_IN pin is held high, the open drain RST_OUT pin will be pulled actively low until is achieved. When occurs, the RST_OUT LOCK is released and a resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the RST_OUT LOCK pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high. Description of the RST_IN/RST_OUT LOCK Functionality The RST_IN and RST_OUT LOCK pins provide a 68030/040/060 processor reset function, with the RST_OUT pin also acting as a lock indicator. If the RST_IN pin is held high during system the RST_OUT pin will be in the low state until steady state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after is achieved the RST_OUT LOCK pin will go into a high impedance state, allowing it to be pulled high by an external resistor see the AC/DC specs for the characteristics of the RST_OUT LOCK pin . If the RST_IN pin is held low during the RST_OUT LOCK pin will remain low. 05/01 Motorola, Inc. 2001 MC88LV926 Pinout Wide SOIC Package Top View 20 GND VCC 2 MR 3 RST_IN 4 VCC AN 5 RC1 6 GND AN 7 SYNC 8 GND 9 Q0 10 19 2X_Q 18 QCLKEN 17 VCC 16 Q2 15 GND 14 RST_OUT LOCK 13 PLL_EN 12 Q1 11 VCC Description of the RST_IN/RST_OUT LOCK Functionality continued After the system is complete and the 88LV926 is to the SYNC input signal RST_OUT high , the processor reset functionality can be utilized. When the RST_IN pin is toggled low min. pulse width=10nS , RST_OUT LOCK will go to the low state and remain there for 1024 cycles of the ‘Q’ output frequency 512 SYNC cycles . During the time in which the RST_OUT LOCK is actively pulled low, all the 88LV926 clock outputs will continue operating correctly and in a locked condition to the SYNC input clock signals to the 68030/040/060 family of processors must continue while the processor is in reset . A propagation delay after the 1024th cycle RST_OUT LOCK goes back to the high impedance state to be pulled high by the resistor. Power Supply Ramp Rate Restriction for Correct 030/040 Processor Reset Operation During System Because the RST_OUT LOCK pin is an indicator of to the reference source, some constraints must be placed on the power supply ramp rate to make sure the RST_OUT LOCK signal holds the processor in reset during system With the recommended loop filter values see Figure the lock time is approximately 10ms. The loop will begin attempting to lock to a reference source if it is present when VCC reaches 2V. If the VCC ramp rate is significantly slower than 10ms, then the PLL could lock to the reference source, causing RST_OUT LOCK to go high before the 88LV926 and ’030/040 processor is fully powered up, violating the processor reset specification. Therefore, if it is necessary for the RST_IN pin to be held high during the VCC ramp rate must be less than 10mS for proper 68030/040/060 reset operation. This ramp rate restriction can be ignored if the RST_IN pin can be held low during system which holds RST_OUT low . The RST_OUT LOCK pin will then be pulled back high 1024 cycles after the RST_IN pin goes high. CAPACITANCE AND POWER SPECIFICATIONS Symbol CIN CPD PD1 Parameter Input Capacitance Power Dissipation Capacitance Power Dissipation at 33MHz With Thevenin Termination

PDF Datasheet Preview

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MC88LV926/D

Low Skew CMOS PLL 68060 Clock Driver

MC88LV926

The MC88LV926 Clock Driver utilizes loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST_IN/RST_OUT LOCK pins provide a processor reset function designed specifically for the MC68/EC/LC030/040/060 microprocessor family. To support the 68060 processor, the 88LV926 operates from a 3.3V as well as a 5.0V supply.

The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88LV926 to multiply a low frequency input clock and distribute it locally at a higher 2X system frequency.

LOW SKEW CMOS PLL 68060 CLOCK DRIVER
• 2X_Q Output Meets All Requirements of the 50 and 66MHz 68060 Microprocessor PCLK Input Specifications
• Low Voltage 3.3V VCC
• Three Outputs With Skew <500ps
• CLKEN Output for Half Speed Bus Applications
• The Phase Variation From Between SYNC and the ‘Q’ Outputs Is Less Than 600ps Derived From the TPD Specification, Which Defines the Skew

DW SUFFIX PLASTIC SOIC PACKAGE

CASE 751D
• SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4
• All Outputs Have ±36mA Drive Equal High and Low CMOS Levels
• Can Drive Either CMOS or TTL Inputs. All Inputs Are Compatible with VCC = 3.3V
• Test Mode Pin PLL_EN Provided for Low Frequency Testing

Three ‘Q’ outputs are provided with less than 500ps skew between their rising edges. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output is ideal for 68060 systems which require a 2X processor clock input, and it meets the tight duty cycle spec of the 50 and 66MHz The QCLKEN output is designed to drive the CLKEN input of the 68060 when the bus logic runs at half of the microprocessor clock rate. The QCLKEN output is skewed relative to the 2X_Q output to ensure that CLKEN setup and hold times of the 68060 are satisfied. A Q/2 frequency is fed back internally, providing a fixed 2X multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally no external feedback pin is provided the input/output frequency relationships are fixed. The Q3 output provides an inverted clock output to allow flexibility in the clock tree design.

In normal operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88LV926 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment.

The RST_OUT LOCK pin doubles as a indicator. When the RST_IN pin is held high, the open drain RST_OUT pin will be pulled actively low until is achieved. When occurs, the RST_OUT LOCK is released and a resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the RST_OUT LOCK pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high.

Description of the RST_IN/RST_OUT LOCK Functionality

The RST_IN and RST_OUT LOCK pins provide a 68030/040/060 processor reset function, with the RST_OUT pin also acting as a lock indicator. If the RST_IN pin is held high during system the RST_OUT pin will be in the low state until steady state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after is achieved the RST_OUT LOCK pin will go into a high impedance state, allowing it to be pulled high by an external resistor see the AC/DC specs for the characteristics of the RST_OUT LOCK pin . If the RST_IN pin is held low during the RST_OUT LOCK pin will remain low.
05/01

Motorola, Inc. 2001

MC88LV926

Pinout Wide SOIC Package Top View
20 GND

VCC 2 MR 3 RST_IN 4 VCC AN 5 RC1 6 GND AN 7 SYNC 8 GND 9 Q0 10
19 2X_Q 18 QCLKEN 17 VCC 16 Q2 15 GND 14 RST_OUT LOCK 13 PLL_EN 12 Q1 11 VCC

Description of the RST_IN/RST_OUT LOCK Functionality continued

After the system is complete and the 88LV926 is to the SYNC input signal RST_OUT high , the processor reset functionality can be utilized. When the RST_IN pin is toggled low min. pulse width=10nS , RST_OUT LOCK will go to the low state and remain there for 1024 cycles of the ‘Q’ output frequency 512 SYNC cycles . During the time in which the RST_OUT LOCK is actively pulled low, all the 88LV926 clock outputs will continue operating correctly and in a locked condition to the SYNC input clock signals to the 68030/040/060 family of processors must continue while the processor is in reset . A propagation delay after the 1024th cycle RST_OUT LOCK goes back to the high impedance state to be pulled high by the resistor.

Power Supply Ramp Rate Restriction for Correct 030/040 Processor Reset Operation During System

Because the RST_OUT LOCK pin is an indicator of
to the reference source, some constraints must be placed on the power supply ramp rate to make sure the RST_OUT LOCK signal holds the processor in reset during system With the recommended loop filter values see Figure the lock time is approximately 10ms. The loop will begin attempting to lock to a reference source if it is present when VCC reaches 2V. If the VCC ramp rate is significantly slower than 10ms, then the PLL could lock to the reference source, causing RST_OUT LOCK to go high before the 88LV926 and ’030/040 processor is fully powered up, violating the processor reset specification. Therefore, if it is necessary for the RST_IN pin to be held high during the VCC ramp rate must be less than 10mS for proper 68030/040/060 reset operation.

This ramp rate restriction can be ignored if the RST_IN pin can be held low during system which holds RST_OUT low . The RST_OUT LOCK pin will then be pulled back high 1024 cycles after the RST_IN pin goes high.

CAPACITANCE AND POWER SPECIFICATIONS

Symbol CIN CPD PD1

Parameter

Input Capacitance

Power Dissipation Capacitance

Power Dissipation at 33MHz With Thevenin Termination

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MC88LV926DWR2 Datasheet file may be downloaded here without warranties.

Datasheet ID: MC88LV926DWR2 635503