MC88915TFN100

MC88915TFN100 Datasheet


Order Number MC88915T/D Rev 5, 08/2001

Part Datasheet
MC88915TFN100 MC88915TFN100 MC88915TFN100 (pdf)
Related Parts Information
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MC88915TFN100R2 MC88915TFN100R2 MC88915TFN100R2
MC88915TFN70 MC88915TFN70 MC88915TFN70
MC88915TFN160 MC88915TFN160 MC88915TFN160
MC88915TFN55 MC88915TFN55 MC88915TFN55
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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MC88915TFN55

Low Skew CMOS PLL

MC88915TFN70

Clock Drivers, 3-State

MC88915TFN100
55, 70, 100, 133 and 160MHz Versions

MC88915TFN133

The MC88915T Clock Driver utilizes loop technology to

MC88915TFN160
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for high performance PC’s
and workstations. For a 3.3V version, see the MC88LV915T data sheet.

The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the MC88915T to multiply a

LOW SKEW CMOS PLL CLOCK DRIVER
low frequency input clock and distribute it locally at a higher 2X system
frequency. Multiple 88915’s can lock onto a single reference clock, which is
ideal for applications when a central system clock must be distributed
synchronously to multiple boards see Figure

Five “Q” outputs are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted 180°
phase shift from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”
frequency.

The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax specification. The wiring diagrams in Figure 5 detail the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the
“Q” outputs to the SYNC input are 2:1, 1:1, and

The FREQ_SEL pin provides one bit programmable in the feedback path of the PLL. It selects between
and of the VCO before its signal reaches the internal clock distribution section of the chip see the block diagram on
page In most applications FREQ_SEL should be held high If a low frequency reference clock input is used, holding

FREQ_SEL low ÷2 will allow the VCO to run in its optimal range >20MHz and >40MHz for the TFN133 version .

In normal operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88915 in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency
board test environment. The second SYNC input can be used as a test clock input to further simplify testing see
detailed description on page

Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q5 and Q/2 into a high impedance state After the

OE/RST pin goes back high Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC
input. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse.

A lock indicator output LOCK will go high when the loop is in phase and frequency lock. The LOCK output will go
low if is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88915 sees a

SYNC signal and full 5V VCC.
• Five Outputs with Skew < 500 ps each being phase and frequency locked to the SYNC input
• The phase variation from between the SYNC and FEEDBACK inputs is less than 550 ps derived from the tPD
specification, which defines the skew
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Datasheet ID: MC88915TFN100 635499