MC68HC711E9CFNE2

MC68HC711E9CFNE2 Datasheet

MC68HC11E Family

Part	Datasheet
MC68HC711E9CFNE2	MC68HC711E9CFNE2 (pdf)

Related Parts	Information
MC68S711E9CFN2	MC68S711E9CFN2

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68HC11M6 HC11M68HC 1M68HC11 M68HC11E/D REV M68HC11E Family Technical Data HCMOS Microcontroller Unit blank MC68HC11E Family Technical Data Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. H8%'C8 HPUPSPG6 Motorola, Inc., 2001 Date May, 2001 June, 2001 System Configuration Register Addition to NOCOP bit description Added EPROM Characteristics EPROM Characteristics For clarity, addition to note 2 following the table Page Number s phyÃ # H8%'C8 HPUPSPG6 Technical Data M68HC11E Family List of Sections Section General Description 23 Section Pin Descriptions 27 Section Central Processor Unit CPU 45 Section Operating Modes and On-Chip Memory 65 Section Resets and Interrupts 107 Section Parallel Input/Output I/O Ports 133 Section Serial Communications Interface SCI 145 Section Serial Peripheral Interface SPI . 165 Section Timing System. 177 Section Analog-to-Digital A/D Converter 209 Section Electrical Characteristics 221 Section Mechanical Data 253 Section Ordering Information 261 Appendix A. Development Support 269 Appendix B. EVBU Schematic 275 List of Sections Technical Data 5 List of Sections AN1060 M68HC11 Bootstrap Mode 277 EB184 Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR 323 EB188 Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR 327 EB296 Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU 331 Technical Data 6 List of Sections Technical Data M68HC11E Family Table of Contents Section General Description Contents 23 Introduction 23 Features 24 Structure 25 Section Pin Descriptions Contents 27 Introduction 28 VDD and VSS 32 RESET 34 Crystal Driver and External Clock Input XTAL and EXTAL 35 E-Clock Output E 36 Interrupt Request IRQ 36 Non-Maskable Interrupt XIRQ/VPPE . MODA and MODB MODA/LIR and MODB/VSTBY 37 VRL and VRH 38 STRA/AS 38 STRB/R/W 38 Port Signals 39 Port A 39 Port B 41 Port C 42 Port D 43 Port E 43 Table of Contents Technical Data 7 Table of Contents Section Central Processor Unit CPU Contents 45 Introduction 46 CPU Registers 46 Accumulators A, B, and D 47 Index Register X IX 48 Index Register Y IY 48 Stack Pointer SP 48 Program Counter PC Condition Code Register CCR 51 Carry/Borrow C 51 Overflow V 51 Zero Z Negative N 52 Interrupt Mask I 52 Half Carry H X Interrupt Mask X STOP Disable S 53 Data Types 53 Opcodes and Operands 53 Addressing Modes 54 Immediate. 54 Direct 55 Extended 55 Indexed. 55 Inherent 55 Relative 56 Instruction Set. Technical Data 8 Table of Contents Table of Contents Section Operating Modes and On-Chip Memory Contents 65 Introduction 66 Section Ordering Information Contents 261 Introduction 261 Standard Device Ordering Information 262 Custom ROM Device Ordering Information 265 Extended Voltage Device Ordering Information Vdc to Vdc 267 Appendix A. Development Support A.1 Contents 269 A.2 Introduction 269 A.3 Motorola M68HC11 E-Series Development Tools A.4 EVS Evaluation System 270 A.5 Motorola Modular Development System MMDS11 271 A.6 SPGMR11 Serial Programmer for M68HC11 MCUs Appendix B. EVBU Schematic M68HC11EVBU Schematic. 275 Table of Contents Technical Data 15 Table of Contents AN1060 AN1060 M68HC11 Bootstrap Mode 277 EB184 EB184 Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR 323 EB188 EB188 Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR 327 EB296 EB296 Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU 331 Technical Data 16 Table of Contents Technical Data M68HC11E Family List of Figures Figure 1-1 M68HC11 E-Series Block Diagram 26 2-1 Pin Assignments for 52-Pin PLCC and CLCC 28 2-2 Pin Assignments for 64-Pin QFP 29 2-3 Pin Assignments for 52-Pin TQFP 30 2-4 Pin Assignments for 56-Pin SDIP. 31 2-5 Pin Assignments for 48-Pin DIP MC68HC811E2 . 32 2-6 External Reset Circuit. 33 2-7 External Reset Circuit with Delay 33 2-8 Common Parallel Resonant Crystal Connections 35 2-9 External Oscillator Connections 35 3-1 Programming Model 47 3-2 Stacking Operations 49 4-1 4-2 4-3 4-4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 Address/Data Demultiplexing 68 Memory Map for MC68HC11E0 70 Memory Map for MC68HC11E1 70 Memory Map for MC68HC 7 11E9. 71 Memory Map for MC68HC 7 11E20. Memory Map for MC68HC811E2 72 Register and Control Bit Assignments 72 RAM Standby MODB/VSTBY Connections 81 Highest Priority I-Bit Interrupt and Miscellaneous Register HPRIO 83 System Configuration Register CONFIG MC68HC811E2 System Configuration Register CONFIG 87 RAM and I/O Mapping Register INIT 89 List of Figures Technical Data 17 List of Figures Technical Data 18 Figure 4-13 4-14 4-15 4-16 4-17 System Configuration Options Register OPTION 91 EPROM and EEPROM Programming Control Register PPROG MC68HC711E20 EPROM Programming An enhanced security feature which protects EPROM contents, RAM, and EEPROM from unauthorized accesses is available in MC68S711E9. Refer to Section Mechanical Data and Section Ordering Information for the exact part number. For further information, these engineering bulletins have been included at the back of this data book: • EB183 Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR • EB188 Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR Operating Modes and On-Chip Memory Technical Data 105 Operating Modes and On-Chip Memory Technical Data 106 Operating Modes and On-Chip Memory Technical Data M68HC11E Family Section Resets and Interrupts Contents Introduction 108 Resets. 108 Power-On Reset POR 109 External Reset 109 Computer Operating Properly COP Reset 110 Clock Monitor Reset 111 System Configuration Options Register 112 Configuration Control Register 113 Effects of Reset 114 Central Processor Unit CPU 115 Memory Map 115 Timer 115 Real-Time Interrupt RTI 116 Pulse Accumulator 116 Computer Operating Properly COP 116 Serial Communications Interface SCI 116 Serial Peripheral Interface SPI . 117 Analog-to-Digital A/D Converter. 117 System 117 Reset and Interrupt Priority. 117 Highest Priority Interrupt and Miscellaneous Register 119 Interrupts. 121 Interrupt Recognition and Register Stacking 122 Non-Maskable Interrupt Request XIRQ Illegal Opcode Trap 123 Software Interrupt SWI . 124 Maskable Interrupts 124 Reset and Interrupt Processing 124 Resets and Interrupts Technical Data 107 Resets and Interrupts Low-Power Operation 129 Wait Mode Stop Mode Introduction Resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched. A reset immediately stops execution of the current instruction and forces the program counter to a known starting address. Internal registers and control bits are initialized so the MCU can resume executing instructions. An interrupt temporarily suspends normal program execution while an interrupt service routine is being executed. After an interrupt has been serviced, the main program resumes as if there had been no interruption. Resets The four possible sources of reset are • Power-on reset POR • External reset • Computer operating properly COP reset • Clock monitor reset POR and RESET share the normal reset vector. COP reset and the clock monitor reset each has its own vector. Technical Data 108 Resets and Interrupts Resets and Interrupts Resets Power-On Reset POR A positive transition on VDD generates a power-on reset POR , which is used only for power-up conditions. POR cannot be used to detect drops in power supply voltages. A 4064 tcyc internal clock cycle delay after the oscillator becomes active allows the clock generator to stabilize. If RESET is at logical 0 at the end of 4064 tcyc, the CPU remains in the reset condition until RESET goes to logical The POR circuit only initializes internal circuitry during cold starts. Refer to Figure External Reset Circuit. NOTE: It is important to protect the MCU during power transitions. Most M68HC11 systems need an external circuit that holds the RESET pin low whenever VDD is below the minimum operating level. This external voltage level detector, or other external reset circuits, are the usual source of reset in a system. External Reset The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than two E-clock cycles after an internal device releases reset. When a reset condition is sensed, the RESET pin is driven low by an internal device for four E-clock cycles, then released. Two E-clock cycles later it is sampled. If the pin is still held low, the CPU assumes that an external reset has occurred. If the pin is high, it indicates that the reset was initiated internally by either the COP system or the clock monitor. CAUTION: Do not connect an external resistor capacitor RC power-up delay circuit to the reset pin of M68HC11 devices because the circuit charge time constant can cause the device to misinterpret the type of reset that occurred. Resets and Interrupts Section Ordering Information Contents Introduction 261 Standard Device Ordering Information 262 Custom ROM Device Ordering Information 265 Extended Voltage Device Ordering Information Vdc to Vdc 267 Introduction This section provides ordering information for the E-series devices. Information is grouped by: • Standard devices • Custom ROM devices • Extended voltage devices Ordering Information Technical Data 261 Ordering Information Standard Device Ordering Information CONFIG 52-pin plastic leaded chip carrier PLCC Temperature BUFFALO ROM to +85°C No ROM to +85°C to +105°C to +125°C No ROM, no EEPROM to +85°C to +105°C to +125°C to +85°C OTPROM to +105°C to +125°C OTPROM, enhanced security feature to +85°C 0°C to +70°C 20 Kbytes OTPROM to +85°C to +105°C to +125°C 0°C to +70°C to +85°C No ROM, 2 Kbytes EEPROM to +105°C to +125°C Frequency 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz 2 MHz 3 MHz 2 MHz 2 MHz 2 MHz 3 MHz 2 MHz 2 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz 2 MHz 2 MHz 2 MHz 2 MHz MC Order Number MC68HC11E9BCFN2 MC68HC11E9BCFN3 MC68HC11E1CFN2 MC68HC11E1CFN3 MC68HC11E1VFN2 MC68HC11E1MFN2 MC68HC11E0CFN2 MC68HC11E0CFN3 MC68HC11E0VFN2 MC68HC11E0MFN2 MC68HC711E9CFN2 MC68HC711E9CFN3 MC68HC711E9VFN2 MC68HC711E9MFN2 MC68S711E9CFN2 MC68HC711E20FN3 MC68HC711E20CFN2 MC68HC711E20CFN3 MC68HC711E20VFN2 MC68HC711E20MFN2 MC68HC811E2FN2 MC68HC811E2CFN2 MC68HC811E2VFN2 MC68HC811E2MFN2 Technical Data 262 Ordering Information Ordering Information Standard Device Ordering Information Description 64-pin quad flat pack QFP CONFIG Temperature BUFFALO ROM to +85°C No ROM No ROM, no EEPROM to +85°C to +105°C to +85°C to +105°C 0°C to +70°°C 20 Kbytes OTPROM 52-pin thin quad flat pack TQFP to +85°C to +105°C to +125°C BUFFALO ROM to +85°C 52-pin windowed ceramic leaded chip carrier CLCC EPROM to +85°C to +105°C to +125°C 0°C o +70°°C 20 Kbytes EPROM to +85°C to +105°C to +125°C Frequency 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz MC Order Number MC68HC11E9BCFU2 MC68HC11E9BCFU3 MC68HC11E1CFU2 MC68HC11E1CFU3 MC68HC11E1VFU2 MC68HC11E0CFU2 MC68HC11E0VFU2 MC68HC711E20FU3 MC68HC711E20CFU2 MC68HC711E20CFU3 MC68HC711E20VFU2 MC68HC711E20MFU2 MC68HC11E9BCPB2 MC68HC11E9BCPB3 MC68HC711E9CFS2 MC68HC711E9CFS3 MC68HC711E9VFS2 MC68HC711E20FS3 MC68HC711E20CFS2 MC68HC711E20CFS3 MC68HC711E20VFS2 MC68HC711E20MFS2 Ordering Information Technical Data 263 Ordering Information CONFIG Temperature Frequency 48-pin dual in-line package DIP MC68HC811E2 only 0°C to +70°°C 2 MHz to +85°C No ROM, 2 Kbytes EEPROM to +105°C 2 MHz 2 MHz to +125°C 2 MHz 56-pin dual in-line package with 0.70-inch lead spacing SDIP BUFFALO ROM to +85°C 2 MHz 3 MHz No ROM to +85°C to +105°C 2 MHz 3 MHz 2 MHz to +125°C 2 MHz No ROM, no EEPROM to +85°C to +105°C 2 MHz 3 MHz 2 MHz to +125°C 2 MHz MC Order Number MC68HC811E2P2 MC68HC811E2CP2 MC68HC811E2VP2 MC68HC811E2MP2 MC68HC11E9BCB2 MC68HC11E9BCB3 MC68HC11E1CB2 MC68HC11E1CB3 MC68HC11E1VB2 MC68HC11E1MB2 MC68HC11E0CB2 MC68HC11E0CB3 MC68HC11E0VB2 MC68HC11E0MB2 Technical Data 264 Ordering Information Ordering Information Custom ROM Device Ordering Information Custom ROM Device Ordering Information Temperature 52-pin plastic leaded chip carrier PLCC 0°C to +70°°C Custom ROM to +85°C to +105°C to +125°C 0°C to +70°°C 20 Kbytes custom ROM 64-pin quad flat pack QFP to +85°C to +105°C to +125°C 0°C to +70°°C Custom ROM to +85°C to +105°C to +125°C 64-pin quad flat pack continued 0°C to +70°°C 20 Kbytes Custom ROM to +85°C to +105°C to +125°C Frequency 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz MC Order Number MC68HC11E9FN3 MC68HC11E9CFN2 MC68HC11E9CFN3 MC68HC11E9VFN2 MC68HC11E9MFN2 MC68HC11E20FN3 MC68HC11E20CFN2 MC68HC11E20CFN3 MC68HC11E20VFN2 MC68HC11E20MFN2 MC68HC11E9FU3 MC68HC11E9CFU2 MC68HC11E9CFU3 MC68HC11E9VFU2 MC68HC11E9MFU2 MC68HC11E20FU3 MC68HC11E20CFU2 MC68HC11E20CFU3 MC68HC11E20VFU2 MC68HC11E20MFU2 Ordering Information Technical Data 265 Ordering Information Temperature Frequency 52-pin thin quad flat pack 10 mm x 10 mm 0°C to +70°°C 3 MHz Custom ROM to +85°C 2 MHz 3 MHz to +105°C 2 MHz to +125°C 2 MHz 56-pin dual in-line package with 0.70-inch lead spacing SDIP 0°C to +70°°C 3 MHz Custom ROM to +85°C 2 MHz 3 MHz to +105°C 2 MHz to +125°C 2 MHz MC Order Number MC68HC11E9PB3 MC68HC11E9CPB2 MC68HC11E9CPB3 MC68HC11E9VPB2 MC68HC11E9MPB2 MC68HC11E9B3 MC68HC11E9CB2 MC68HC11E9CB3 MC68HC11E9VB2 MC68HC11E9MB2 Technical Data 266 Ordering Information Ordering Information Extended Voltage Device Ordering Information Vdc to Vdc Extended Voltage Device Ordering Information Vdc to Vdc Temperature Frequency 52-pin plastic leaded chip carrier PLCC Custom ROM 2 MHz No ROM to +70°C 2 MHz No ROM, no EEPROM 2 MHz 64-pin quad flat pack QFP Custom ROM 2 MHz No ROM to +70°C 2 MHz No ROM, no EEPROM 2 MHz 52-pin thin quad flat pack 10 mm x 10 mm Custom ROM 2 MHz No ROM to +70°C 2 MHz No ROM, no EEPROM 2 MHz 56-pin dual in-line package with 0.70-inch lead spacing SDIP Custom ROM 2 MHz No ROM to +70°C 2 MHz No ROM, no EEPROM 2 MHz MC Order Number MC68L11E9FN2 MC68L11E1FN2 MC68L11E0FN2 MC68L11E9FU2 MC68L11E1FU2 MC68L11E0FU2 MC68L11E9PB2 MC68L11E1PB2 MC68L11E0PB2 MC68L11E9B2 MC68L11E1B2 MC68L11E0B2 Ordering Information Technical Data 267 Ordering Information Technical Data 268 Ordering Information Technical Data M68HC11E Family Appendix A. Development Support A.1 Contents A.2 Introduction 269 A.3 Motorola M68HC11 E-Series Development Tools A.4 EVS Evaluation System 270 A.5 Motorola Modular Development System MMDS11 271 A.6 SPGMR11 Serial Programmer for M68HC11 MCUs A.2 Introduction This section provides information on the development support offered for the E-series devices. Development Support Technical Data 269 Development Support A.3 Motorola M68HC11 E-Series Development Tools Device Package Emulation Module 1 2 Flex Cable 1 2 MMDS11 Target Head 1 2 SPGMR Programming Adapter 3 52 FN M68EM11E20 M68CBL11C M68TC11E20FN52 M68PA11E20FN52 MC68HC11E9 MC68HC711E9 52 PB 56 B M68EM11E20 M68CBL11C M68CBL11B M68TC11E20PB52 M68TC11E20B56 M68PA11E20PB52 M68PA11E20B56 64 FU M68EM11E20 M68CBL11C M68TC11E20FU64 M68PA11E20FU64 MC68HC11E20 MC68HC711E20 52 FN 64 FU M68EM11E20 M68CBL11C M68TC11E20FN52 M68TC11E20FU64 M68PA11E20FN52 M68PA11E20FU64 MC68HC811E2 48 P 52 FN M68EM11E20 M68CBL11B M68CBL11C M68TB11E20P48 M68TC11E20FN52 M68PA11A8P48 M68PA11E20FN52 Each MMDS11 system consists of a system console M68MMDS11 , an emulation module, a flex cable, and a target head. A complete EVS consists of a platform board M68HC11PFB , an emulation module, a flex cable, and a target head. Each SPGMR system consists of a universal serial programmer M68SPGMR11 and a programming adapter. It can be used alone or in conjunction with the MMDS11. A.4 EVS Evaluation System

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68HC11M6 HC11M68HC
1M68HC11

M68HC11E/D REV

M68HC11E Family Technical Data

HCMOS Microcontroller Unit
blank

MC68HC11E Family

Technical Data

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc.

H8%'C8 HPUPSPG6

Motorola, Inc., 2001

Date May, 2001 June, 2001

System Configuration Register Addition to NOCOP
bit description

Added EPROM Characteristics

EPROM Characteristics For clarity, addition to note 2 following the table

Page Number s
phyÃ #

H8%'C8 HPUPSPG6

Technical Data M68HC11E Family

List of Sections
Section General Description 23 Section Pin Descriptions 27 Section Central Processor Unit CPU 45 Section Operating Modes and On-Chip Memory 65 Section Resets and Interrupts 107 Section Parallel Input/Output I/O Ports 133 Section Serial Communications Interface SCI 145 Section Serial Peripheral Interface SPI . 165 Section Timing System. 177 Section Analog-to-Digital A/D Converter 209 Section Electrical Characteristics 221 Section Mechanical Data 253 Section Ordering Information 261 Appendix A. Development Support 269 Appendix B. EVBU Schematic 275

List of Sections

Technical Data 5

List of Sections

AN1060 M68HC11 Bootstrap Mode 277

EB184 Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR 323

EB188 Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR 327

EB296 Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU 331

Technical Data 6

List of Sections

Technical Data M68HC11E Family

Table of Contents

Section General Description

Contents 23 Introduction 23 Features 24 Structure 25

Section Pin Descriptions

Contents 27

Introduction 28

VDD and VSS 32 RESET 34

Crystal Driver and External Clock Input XTAL and EXTAL 35

E-Clock Output E 36

Interrupt Request IRQ 36

Non-Maskable Interrupt XIRQ/VPPE . MODA and MODB MODA/LIR and MODB/VSTBY 37 VRL and VRH 38 STRA/AS 38

STRB/R/W 38

Port Signals 39 Port A 39 Port B 41 Port C 42 Port D 43 Port E 43

Table of Contents

Technical Data 7

Table of Contents

Section Central Processor Unit CPU

Contents 45

Introduction 46

CPU Registers 46 Accumulators A, B, and D 47 Index Register X IX 48 Index Register Y IY 48 Stack Pointer SP 48 Program Counter PC Condition Code Register CCR 51 Carry/Borrow C 51 Overflow V 51 Zero Z Negative N 52 Interrupt Mask I 52 Half Carry H X Interrupt Mask X STOP Disable S 53

Data Types 53

Opcodes and Operands 53

Addressing Modes 54 Immediate. 54 Direct 55 Extended 55 Indexed. 55 Inherent 55 Relative 56

Instruction Set.

Technical Data 8

Table of Contents

Table of Contents

Section Operating Modes and On-Chip Memory

Contents 65

Introduction 66
Section Ordering Information
Contents 261 Introduction 261 Standard Device Ordering Information 262 Custom ROM Device Ordering Information 265 Extended Voltage Device Ordering Information

Vdc to Vdc 267

Appendix A. Development Support

A.1 Contents 269 A.2 Introduction 269 A.3 Motorola M68HC11 E-Series Development Tools A.4 EVS Evaluation System 270 A.5 Motorola Modular Development System MMDS11 271 A.6 SPGMR11 Serial Programmer for M68HC11 MCUs

Appendix B. EVBU Schematic

M68HC11EVBU Schematic. 275

Table of Contents

Technical Data 15

Table of Contents

AN1060

AN1060 M68HC11 Bootstrap Mode 277

EB184

EB184 Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR 323

EB188

EB188 Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR 327

EB296

EB296 Programming MC68HC711E9 Devices with PCbug11 and the M68HC11EVBU 331

Technical Data 16

Table of Contents

Technical Data M68HC11E Family

List of Figures

Figure
1-1 M68HC11 E-Series Block Diagram 26
2-1 Pin Assignments for 52-Pin PLCC and CLCC 28 2-2 Pin Assignments for 64-Pin QFP 29 2-3 Pin Assignments for 52-Pin TQFP 30 2-4 Pin Assignments for 56-Pin SDIP. 31 2-5 Pin Assignments for 48-Pin DIP MC68HC811E2 . 32 2-6 External Reset Circuit. 33 2-7 External Reset Circuit with Delay 33 2-8 Common Parallel Resonant Crystal Connections 35 2-9 External Oscillator Connections 35
3-1 Programming Model 47 3-2 Stacking Operations 49
4-1 4-2 4-3 4-4-5 4-6 4-7 4-8 4-9
4-10 4-11
4-12

Address/Data Demultiplexing 68 Memory Map for MC68HC11E0 70 Memory Map for MC68HC11E1 70 Memory Map for MC68HC 7 11E9. 71 Memory Map for MC68HC 7 11E20. Memory Map for MC68HC811E2 72 Register and Control Bit Assignments 72 RAM Standby MODB/VSTBY Connections 81 Highest Priority I-Bit Interrupt and Miscellaneous

Register HPRIO 83 System Configuration Register CONFIG MC68HC811E2 System Configuration

Register CONFIG 87 RAM and I/O Mapping Register INIT 89

List of Figures

Technical Data 17

List of Figures

Technical Data 18

Figure
4-13 4-14
4-15
4-16 4-17

System Configuration Options Register OPTION 91 EPROM and EEPROM Programming

Control Register PPROG MC68HC711E20 EPROM Programming
An enhanced security feature which protects EPROM contents, RAM, and EEPROM from unauthorized accesses is available in MC68S711E9. Refer to Section Mechanical Data and Section Ordering Information for the exact part number.

For further information, these engineering bulletins have been included at the back of this data book:
• EB183 Enabling the Security Feature on the MC68HC711E9 Devices with PCbug11 on the M68HC711E9PGMR
• EB188 Enabling the Security Feature on M68HC811E2 Devices with PCbug11 on the M68HC711E9PGMR

Operating Modes and On-Chip Memory

Technical Data 105

Operating Modes and On-Chip Memory

Technical Data 106

Operating Modes and On-Chip Memory

Technical Data M68HC11E Family

Section Resets and Interrupts

Contents

Introduction 108

Resets. 108 Power-On Reset POR 109 External Reset 109 Computer Operating Properly COP Reset 110 Clock Monitor Reset 111 System Configuration Options Register 112 Configuration Control Register 113

Effects of Reset 114 Central Processor Unit CPU 115 Memory Map 115 Timer 115 Real-Time Interrupt RTI 116 Pulse Accumulator 116 Computer Operating Properly COP 116 Serial Communications Interface SCI 116 Serial Peripheral Interface SPI . 117 Analog-to-Digital A/D Converter. 117 System 117

Reset and Interrupt Priority. 117 Highest Priority Interrupt and Miscellaneous Register 119

Interrupts. 121 Interrupt Recognition and Register Stacking 122 Non-Maskable Interrupt Request XIRQ Illegal Opcode Trap 123 Software Interrupt SWI . 124 Maskable Interrupts 124 Reset and Interrupt Processing 124

Resets and Interrupts

Technical Data 107

Resets and Interrupts

Low-Power Operation 129 Wait Mode Stop Mode

Introduction

Resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched. A reset immediately stops execution of the current instruction and forces the program counter to a known starting address. Internal registers and control bits are initialized so the MCU can resume executing instructions. An interrupt temporarily suspends normal program execution while an interrupt service routine is being executed. After an interrupt has been serviced, the main program resumes as if there had been no interruption.

Resets

The four possible sources of reset are
• Power-on reset POR
• External reset
• Computer operating properly COP reset
• Clock monitor reset

POR and RESET share the normal reset vector. COP reset and the clock monitor reset each has its own vector.

Technical Data 108

Resets and Interrupts

Resets and Interrupts Resets

Power-On Reset POR

A positive transition on VDD generates a power-on reset POR , which is used only for power-up conditions. POR cannot be used to detect drops
in power supply voltages. A 4064 tcyc internal clock cycle delay after the oscillator becomes active allows the clock generator to stabilize. If

RESET is at logical 0 at the end of 4064 tcyc, the CPU remains in the reset condition until RESET goes to logical

The POR circuit only initializes internal circuitry during cold starts. Refer to Figure External Reset Circuit.

NOTE:

It is important to protect the MCU during power transitions. Most M68HC11 systems need an external circuit that holds the RESET pin low whenever VDD is below the minimum operating level. This external voltage level detector, or other external reset circuits, are the usual source of reset in a system.

External Reset

The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than two E-clock cycles after an internal device releases reset. When a reset condition is sensed, the RESET pin is driven low by an internal device for four E-clock cycles, then released. Two E-clock cycles later it is sampled. If the pin is still held low, the CPU assumes that an external reset has occurred. If the pin is high, it indicates that the reset was initiated internally by either the COP system or the clock monitor.

CAUTION:

Do not connect an external resistor capacitor RC power-up delay circuit to the reset pin of M68HC11 devices because the circuit charge time constant can cause the device to misinterpret the type of reset that occurred.

Resets and Interrupts
Section Ordering Information

Contents
Introduction 261 Standard Device Ordering Information 262 Custom ROM Device Ordering Information 265 Extended Voltage Device Ordering

Information Vdc to Vdc 267

Introduction
This section provides ordering information for the E-series devices. Information is grouped by:
• Standard devices
• Custom ROM devices
• Extended voltage devices
Ordering Information

Technical Data 261
Ordering Information
Standard Device Ordering Information

CONFIG
52-pin plastic leaded chip carrier PLCC

Temperature

BUFFALO ROM
to +85°C

No ROM
to +85°C
to +105°C
to +125°C

No ROM, no EEPROM
to +85°C
to +105°C
to +125°C
to +85°C

OTPROM
to +105°C
to +125°C

OTPROM, enhanced security feature
to +85°C
0°C to +70°C
20 Kbytes OTPROM
to +85°C
to +105°C
to +125°C
0°C to +70°C
to +85°C

No ROM, 2 Kbytes EEPROM
to +105°C
to +125°C

Frequency
2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz 2 MHz 3 MHz 2 MHz 2 MHz 2 MHz 3 MHz 2 MHz 2 MHz
2 MHz
3 MHz 2 MHz 3 MHz 2 MHz 2 MHz 2 MHz 2 MHz 2 MHz 2 MHz

MC Order Number

MC68HC11E9BCFN2 MC68HC11E9BCFN3 MC68HC11E1CFN2 MC68HC11E1CFN3 MC68HC11E1VFN2 MC68HC11E1MFN2 MC68HC11E0CFN2 MC68HC11E0CFN3 MC68HC11E0VFN2 MC68HC11E0MFN2 MC68HC711E9CFN2 MC68HC711E9CFN3 MC68HC711E9VFN2 MC68HC711E9MFN2

MC68S711E9CFN2

MC68HC711E20FN3 MC68HC711E20CFN2 MC68HC711E20CFN3 MC68HC711E20VFN2 MC68HC711E20MFN2

MC68HC811E2FN2 MC68HC811E2CFN2 MC68HC811E2VFN2 MC68HC811E2MFN2

Technical Data 262
Ordering Information
Ordering Information Standard Device Ordering Information

Description 64-pin quad flat pack QFP

CONFIG

Temperature

BUFFALO ROM
to +85°C

No ROM No ROM, no EEPROM
to +85°C
to +105°C
to +85°C
to +105°C
0°C to +70°°C
20 Kbytes OTPROM
52-pin thin quad flat pack TQFP
to +85°C
to +105°C to +125°C

BUFFALO ROM
to +85°C
52-pin windowed ceramic leaded chip carrier CLCC

EPROM
to +85°C
to +105°C
to +125°C
0°C o +70°°C
20 Kbytes EPROM
to +85°C
to +105°C
to +125°C

Frequency
2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz
2 MHz 3 MHz
2 MHz 3 MHz 2 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz

MC Order Number

MC68HC11E9BCFU2 MC68HC11E9BCFU3 MC68HC11E1CFU2 MC68HC11E1CFU3 MC68HC11E1VFU2 MC68HC11E0CFU2 MC68HC11E0VFU2 MC68HC711E20FU3 MC68HC711E20CFU2 MC68HC711E20CFU3 MC68HC711E20VFU2 MC68HC711E20MFU2

MC68HC11E9BCPB2 MC68HC11E9BCPB3

MC68HC711E9CFS2 MC68HC711E9CFS3 MC68HC711E9VFS2 MC68HC711E20FS3 MC68HC711E20CFS2 MC68HC711E20CFS3 MC68HC711E20VFS2 MC68HC711E20MFS2
Ordering Information

Technical Data 263
Ordering Information

CONFIG

Temperature

Frequency
48-pin dual in-line package DIP MC68HC811E2 only
0°C to +70°°C
2 MHz
to +85°C

No ROM, 2 Kbytes EEPROM
to +105°C
2 MHz 2 MHz
to +125°C
2 MHz
56-pin dual in-line package with 0.70-inch lead spacing SDIP

BUFFALO ROM
to +85°C
2 MHz 3 MHz

No ROM
to +85°C
to +105°C
2 MHz 3 MHz 2 MHz
to +125°C
2 MHz

No ROM, no EEPROM
to +85°C
to +105°C
2 MHz 3 MHz 2 MHz
to +125°C
2 MHz

MC Order Number

MC68HC811E2P2 MC68HC811E2CP2 MC68HC811E2VP2 MC68HC811E2MP2

MC68HC11E9BCB2 MC68HC11E9BCB3 MC68HC11E1CB2 MC68HC11E1CB3 MC68HC11E1VB2 MC68HC11E1MB2 MC68HC11E0CB2 MC68HC11E0CB3 MC68HC11E0VB2 MC68HC11E0MB2

Technical Data 264
Ordering Information
Ordering Information Custom ROM Device Ordering Information
Custom ROM Device Ordering Information

Temperature
52-pin plastic leaded chip carrier PLCC
0°C to +70°°C

Custom ROM
to +85°C
to +105°C to +125°C
0°C to +70°°C
20 Kbytes custom ROM 64-pin quad flat pack QFP
to +85°C to +105°C to +125°C
0°C to +70°°C

Custom ROM
to +85°C
to +105°C
to +125°C
64-pin quad flat pack continued
0°C to +70°°C
20 Kbytes Custom ROM
to +85°C
to +105°C to +125°C

Frequency
3 MHz 2 MHz 3 MHz 2 MHz 2 MHz 3 MHz 2 MHz 3 MHz 2 MHz 2 MHz
3 MHz 2 MHz 3 MHz 2 MHz 2 MHz
3 MHz 2 MHz 3 MHz 2 MHz 2 MHz

MC Order Number

MC68HC11E9FN3 MC68HC11E9CFN2 MC68HC11E9CFN3 MC68HC11E9VFN2 MC68HC11E9MFN2 MC68HC11E20FN3 MC68HC11E20CFN2 MC68HC11E20CFN3 MC68HC11E20VFN2 MC68HC11E20MFN2

MC68HC11E9FU3 MC68HC11E9CFU2 MC68HC11E9CFU3 MC68HC11E9VFU2 MC68HC11E9MFU2

MC68HC11E20FU3 MC68HC11E20CFU2 MC68HC11E20CFU3 MC68HC11E20VFU2 MC68HC11E20MFU2
Ordering Information

Technical Data 265
Ordering Information

Temperature

Frequency
52-pin thin quad flat pack 10 mm x 10 mm
0°C to +70°°C
3 MHz

Custom ROM
to +85°C
2 MHz 3 MHz
to +105°C
2 MHz
to +125°C
2 MHz
56-pin dual in-line package with 0.70-inch lead spacing SDIP
0°C to +70°°C
3 MHz

Custom ROM
to +85°C
2 MHz 3 MHz
to +105°C
2 MHz
to +125°C
2 MHz

MC Order Number

MC68HC11E9PB3 MC68HC11E9CPB2 MC68HC11E9CPB3 MC68HC11E9VPB2 MC68HC11E9MPB2

MC68HC11E9B3 MC68HC11E9CB2 MC68HC11E9CB3 MC68HC11E9VB2 MC68HC11E9MB2

Technical Data 266
Ordering Information
Ordering Information Extended Voltage Device Ordering Information Vdc to Vdc
Extended Voltage Device Ordering Information Vdc to Vdc

Temperature

Frequency
52-pin plastic leaded chip carrier PLCC

Custom ROM
2 MHz

No ROM
to +70°C
2 MHz

No ROM, no EEPROM
2 MHz
64-pin quad flat pack QFP

Custom ROM
2 MHz

No ROM
to +70°C
2 MHz

No ROM, no EEPROM
2 MHz
52-pin thin quad flat pack 10 mm x 10 mm

Custom ROM
2 MHz

No ROM
to +70°C
2 MHz

No ROM, no EEPROM
2 MHz
56-pin dual in-line package with 0.70-inch lead spacing SDIP

Custom ROM
2 MHz

No ROM
to +70°C
2 MHz

No ROM, no EEPROM
2 MHz

MC Order Number

MC68L11E9FN2 MC68L11E1FN2 MC68L11E0FN2

MC68L11E9FU2 MC68L11E1FU2 MC68L11E0FU2

MC68L11E9PB2 MC68L11E1PB2 MC68L11E0PB2

MC68L11E9B2 MC68L11E1B2 MC68L11E0B2
Ordering Information

Technical Data 267
Ordering Information

Technical Data 268
Ordering Information

Technical Data M68HC11E Family

Appendix A. Development Support

A.1 Contents

A.2 Introduction 269 A.3 Motorola M68HC11 E-Series Development Tools A.4 EVS Evaluation System 270 A.5 Motorola Modular Development System MMDS11 271 A.6 SPGMR11 Serial Programmer for M68HC11 MCUs

A.2 Introduction

This section provides information on the development support offered for the E-series devices.

Development Support

Technical Data 269

Development Support

A.3 Motorola M68HC11 E-Series Development Tools

Device

Package

Emulation Module 1 2

Flex Cable 1 2

MMDS11 Target Head 1 2

SPGMR Programming

Adapter 3
52 FN M68EM11E20 M68CBL11C M68TC11E20FN52 M68PA11E20FN52

MC68HC11E9 MC68HC711E9
52 PB 56 B

M68EM11E20

M68CBL11C M68CBL11B

M68TC11E20PB52 M68TC11E20B56

M68PA11E20PB52 M68PA11E20B56
64 FU M68EM11E20 M68CBL11C M68TC11E20FU64 M68PA11E20FU64

MC68HC11E20 MC68HC711E20
52 FN 64 FU

M68EM11E20

M68CBL11C

M68TC11E20FN52 M68TC11E20FU64

M68PA11E20FN52 M68PA11E20FU64

MC68HC811E2
48 P 52 FN

M68EM11E20

M68CBL11B M68CBL11C

M68TB11E20P48 M68TC11E20FN52

M68PA11A8P48 M68PA11E20FN52

Each MMDS11 system consists of a system console M68MMDS11 , an emulation module, a flex cable, and a target head. A complete EVS consists of a platform board M68HC11PFB , an emulation module, a flex cable, and a target head. Each SPGMR system consists of a universal serial programmer M68SPGMR11 and a programming adapter. It can be
used alone or in conjunction with the MMDS11.

A.4 EVS Evaluation System

More datasheets: MK2041-AL | ASCX100AN | LTW-Z5630SZL57 | LTL-2800G | TMC22153AKHC | 59025-020 | 59020-010 | 59025-030 | 59025-040 | 59025-010

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MC68HC711E9CFNE2 Datasheet file may be downloaded here without warranties.

Datasheet ID: MC68HC711E9CFNE2 635492