MCP11A1CFNE3

MCP11A1CFNE3 Datasheet


Part Datasheet
MCP11A1CFNE3 MCP11A1CFNE3 MCP11A1CFNE3 (pdf)
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MC68HC11A8

HCMOS Single-Chip Microcontroller

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Paragraph Number

Freescale Semiconductor, Inc. TABLE OF CONTENTS

Page Number
1 INTRODUCTION

Features 1-1 Hardware Features 1-1 Software Features 1-1

General Description 1-1 Programmer’s Model 1-2 Summary of M68HC11 Family 1-3
2 SIGNAL DESCRIPTIONS AND OPERATING MODES

Signal Pin Descriptions 2-1

Input Power VDD and Ground VSS 2-1 Reset 2-1

Crystal Driver and External Clock Input XTAL, EXTAL 2-1

E Clock Output E 2-3

Interrupt Request IRQ 2-3

Non-Maskable Interrupt XIRQ 2-3

Mode A/Load Instruction Register and Mode B/Standby Voltage MODA/

LIR, MODB/VSTBY 2-3

A/D Converter Reference Voltages VRL, VRH 2-4

Strobe B and Read/Write STRB/R/W 2-4

Strobe A and Address Strobe STRA/AS 2-4

Port Signals 2-4

Port A 2-5

Port B 2-5

Port C 2-5

Port D 2-5

Port E 2-6

Operating Modes 2-6

Single-Chip Operating Mode 2-6

Expanded Multiplexed Operating Mode 2-6

Special Bootstrap Operating Mode 2-8

Additional Boot Loader Program Options 2-10

Special Test Operating Mode 2-10
3 ON-CHIP MEMORY

Memory Maps 3-1 RAM and I/O Mapping Register INIT 3-4 ROM 3-5 RAM 3-5 EEPROM 3-5
B MECHANICAL DATA AND ORDERING INFORMATION

B.1 Pin Assignments B-1 B.2 Package Dimensions B-3

C DEVELOPMENT SUPPORT

C.1 C.1.1 C.2 C.2.1 C.3 C.3.1 C.4 C.4.1

M68HC11EVB Evaluation Board C-1 EVB Features C-1

M68HC11EVBU Universal Evaluation Board C-1 EVBU Features C-1

M68HC11EVM Evaluation Module C-2 EVM Features C-2

MMDS11 Modular Development System C-2 MMDS11Features C-3

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MC68HC11A8 TECHNICAL DATA

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Figure
1-1 Block Diagram 1-2 1-2 Programming Model 1-3 2-1 Common Crystal Connections 2-2-2 External Oscillator Connections 2-2-3 One Crystal Driving Two MCUs 2-2-4 Address/Data Demultiplexing 2-8 3-1 Memory Maps 3-1 5-1 Data Format 5-2 5-2 Sampling Technique Used on All Bits 5-3 5-3 Examples of Start Bit Sampling Techniques 5-4 5-4 SCI Artificial Start Following a Framing Error 5-4 5-5 SCI Start Bit Following a Break 5-4 5-6 Serial Communications Interface Block Diagram 5-7 5-7 Rate Generator Division 5-12 6-1 Data Clock Timing Diagram 6-2 6-2 Serial Peripheral Interface Block Diagram 6-3 6-3 Serial Peripheral Interface Master-Slave Interconnection 6-4 7-1 A/D Conversion Sequence 7-2 7-2 A/D Pin Model 7-2 9-1 Reset Timing 9-2 9-2 Simple LVI Reset Circuit 9-3 9-3 Interrupt Stacking Order 9-9-4 Processing Flow Out of Resets Sheet 1 of 2 9-12 9-4 Processing Flow Out of Resets Sheet 2 of 2 9-13 9-5 Interrupt Priority Resolution Sheet 1 of 2 9-14 9-5 Interrupt Priority Resolution Sheet 2 of 2 9-15 9-6 Interrupt Source Resolution Within SCI 9-16 10-1 Programming Model 10-2 10-2 Special Operations 10-12 A-1 Test Methods A-4 A-2 Timer Inputs A-7 A-3 POR and External Reset Timing Diagram A-8 A-4 STOP Recovery Timing Diagram A-9 A-5 WAIT Recovery Timing Diagram A-10 A-6 Interrupt Timing Diagram A-11 A-7 Port Write Timing Diagram A-14 A-8 Port Read Timing Diagram A-14 A-9 Simple Output Strobe Timing Diagram A-14 A-10 Simple Input Strobe Timing Diagram A-15 A-11 Port C Input Handshake Timing Diagram A-15 A-12 Port C Output Handshake Timing Diagram A-15 A-13 Three-State Variation of Output Handshake Timing Diagram STRA Enables Output Buffer A-16 A-14 Multiplexed Expansion Bus Timing Diagram A-21 A-8 a SPI Master Timing CPHA = 0 A-24

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A-8 A-15 A-15 A-15 A-15 B-1 B-2 B-3 B-4

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b SPI Master Timing CPHA = 1 A-24 SPI Timing Diagram 1 of 2 A-24 c SPI Slave Timing CPHA = 0 A-25 d SPI Slave Timing CPHA = 1 A-25 SPI Timing Diagrams 2 of 2 A-25 52-Pin PLCC B-1 48-Pin DIP B-2 64-Pin QFP B-3 M68HC11 P/N Options B-5

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MC68HC11A8 TECHNICAL DATA

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Freescale Semiconductor, Inc. LIST OF TABLES

Table
1-1 M68HC11 Family Devices 1-4 2-1 Operating Modes vs. MODA and MODB 2-3 2-2 Port Signal 2-7 2-3 Bootstrap Mode Interrupt 2-9 3-1 Register and Control Bit Assignments 3-2 4-1 Handshake l/O Operations Summary 4-4 5-1 First Prescaler Stage 5-11 5-2 Second Prescaler Stage 5-12 5-3 Prescaler Highest Baud Rate Frequency 5-12 5-4 Transmit Baud Rate Output for a Given Prescaler Output 5-13 6-1 Serial Peripheral Rate 6-5 7-1 Analog-to-Digital Channel Assignments 7-4 8-1 Real Time Interrupt Rate versus RTR1 and RTR0 8-9-1 COP Timeout Period versus CR1 and 9-5 9-2 IRQ Vector 9-8 9-3 Interrupt Vector Assignments 9-8 9-4 SCI Serial System Interrupts 9-9-5 Mode Bits Relationship 9-11 9-6 Highest Priority I Interrupt versus PSEL[3:0] 9-17 9-7 Pin State Summary for RESET, STOP, and 9-18 10-1 MC68HC11A8 Instructions, Addressing Modes, and Execution Times............. 10-6 10-2 Cycle-by-Cycle Operation Inherent Mode 10-13 10-3 Cycle-by-Cycle Operation Immediate Mode 10-16 10-4 Cycle-by-Cycle Operation Direct 10-16 10-5 Cycle-by-Cycle Operation Extended Mode 10-18 10-6 Cycle-by-Cycle Operation Indexed X Mode 10-19 10-7 Cycle-by-Cycle Operation Indexed Y Mode 10-21 10-8 Cycle-by-Cycle Operation Relative Mode 10-22 A-1 Maximum Rating A-1 A-2 Thermal Characteristics A-1 A-3 DC Electrical A-2 A-3 DC Electrical Characteristics MC68L11A8 A-3 A-4 Control Timing A-5 A-4 Control Timing MC68L11A8 A-6 A-5 Peripheral Port A-12 A-5 Peripheral Port Timing MC68L11A8 A-13 A-6 Analog-To-Digital Converter Characteristics A-17 A-6 Analog-To-Digital Converter Characteristics MC68L11A8 A-18 A-7 Expansion Bus A-19 A-7 Expansion Bus Timing MC68L11A8 A-20 A-8 Serial Peripheral Interface SPI A-22 A-8 Serial Peripheral Interface SPI Timing MC68L11A8 A-23

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A-9 EEPROM Characteristics A-26 A-9 EEPROM Characteristics MC68L11A8 A-26 B-1 Ordering Information B-4

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MC68HC11A8 TECHNICAL DATA

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1 INTRODUCTION

The HCMOS MC68HC11A8 is an advanced 8-bit microcontroller MCU with highly sophisticated on-chip peripheral capabilities. A fully static design and high-density complementary metal-oxide semiconductor HCMOS fabrication process allow E-series devices to operate at frequencies from 3 MHz to dc, with very low power consumption.

Features The following are some of the hardware and software highlights.

Hardware Features
• 8 Kbytes of ROM
• 512 Bytes of EEPROM
• 256 Bytes of RAM All Saved During Standby Relocatable to Any 4K Boundary
• Enhanced 16-Bit Timer System:

Four Stage Programmable Prescaler Three Input Capture Functions Five Output Compare Functions
• 8-Bit Pulse Accumulator Circuit
• Enhanced NRZ Serial Communications Interface SCI
• Serial Peripheral Interface SPI
• Eight Channel, 8-Bit Analog-to-Digital Converter
• Real Time Interrupt Circuit
• Computer Operating Properly COP Watchdog System
• Available in Dual-In-Line or Leaded Chip Carrier Packages

Software Features
• Enhanced M6800/M6801 Instruction Set
• 16 x 16 Integer and Fractional Divide Features
• Bit Manipulation
• WAIT Mode
• STOP Mode

The high-density CMOS technology HCMOS used on the MC68HC11A8 combines smaller size and higher speeds with the low power and high noise immunity of CMOS. On-chip memory systems include 8 Kbytes of ROM, 512 bytes of electrically erasable programmable ROM EEPROM , and 256 bytes of static RAM.

A block diagram of the MC68HC11A8 is shown in Figure Major peripheral functions are provided on-chip. An eight channel analog-to-digital A/D converter is included with eight bits of resolution. An asynchronous serial communications interface

TECHNICAL DATA

INTRODUCTION

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MOTOROLA 1-1

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SCI and a separate synchronous serial peripheral interface SPI are included. The main 16-bit free-running timer system has three input capture lines, five output compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods.

Self monitoring circuitry is included on-chip to protect against system errors. A computer operating properly COP watchdog system protects against software failures. A clock monitor system generates a system reset in case the clock is lost or runs too slow. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal opcode is detected.

Two software controlled operating modes, WAIT and STOP, are available to conserve additional power.

PULSE ACCUMULATOR

MODA/ LIR

MODB/ VSTBY

XTAL EXTAL E

MODE CONTROL

OSCILLATOR CLOCK LOGIC

IRQ XIRQ

RESET

INTERRUPT LOGIC

PERIODIC INTERRUPT

TIMER SYSTEM

BUS EXPANSION ADDRESS

ADDRESS/DATA

STROBE AND HANDSHAKE PARALLEL I/O
8 KBYTES ROM
512 BYTES EEPROM
B MECHANICAL DATA AND ORDERING INFORMATION

B.1 Pin Assignments The MC68HC11A8 is available in the 52-pin plastic leaded chip carrier PLCC , the 48pin dual in-line package DIP , or the 64-pin quad flat pack QFP .
47 PE2/AN2
48 PE6/AN6
49 PE3/AN3
50 PE7/AN7

MODA/LIR MODB/VSTBY VSS VRH VRL
4 STRA/AS
6 STRB/R/W 5E
7 EXTAL
3 2 1 52 51

XTAL 8 PC0/A0/D0 9 PC1/A1/D1 10 PC2/A2/D2 11 PC3/A3/D3 12 PC4/A4/D4 13 PC5/A5/D5 14 PC6/A6/D6 15 PC7/A7/D7 16

RESET 17 XIRQ 18 IRQ 19

PD0/RxD 20
46 PE5/AN5 45 PE1/AN1 44 PE4/AN4 43 PE0/AN0 42 PB0/A8 41 PB1/A9 40 PB2/A10 39 PB3/A11 38 PB4/A12 37 PB5/A13 36 PB6/A14 35 PB7/A15 34 PA0/IC3

PD1/TxD 21 PD2/MISO 22 PD3/MOSI 23 PD4/SCK 24

PD5/SS 25 VDD 26

PA7/PAI/OC1 27 PA6/OC2/OC1 28 PA5/OC3/OC1 29 PA4/OC4/OC1 30 PA3/OC5/OC1 31

PA2/IC1 32 PA1/IC2 33

Figure B-1 52-Pin PLCC

A8 52-PIN PLCC

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PA7/PAI/OC1 1 PA6/OC2/OC1 2 PA5/OC3/OC1 3 PA4/OC4/OC1 4 PA3/OC5/OC1 5

PA2/IC1 6 PA1/IC2 7 PA0/IC3 8 PB7/A15 9 PB6/A14 10 PB5/A13 11 PB4/A12 12

PB3/A11 13 PB2/A10 14

PB1/A9 15 PB0/A8 16

PE0/AN0 17 PE1/AN1 18 PE2/AN2 19 PE3/AN3 20

VRL 21 VRH 22 VSS 23 MODB/VSTBY 24
48 VDD 47 PD5/SS 46 PD4/SCK 45 PD3/MOSI 44 PD2/MISO 43 PD1/TxD 42 PD0/RxD 41 IRQ 40 XIRQ 39 RESET 38 PC7/A7/D7 37 PC6/A6/D6 36 PC5/A5/D5 35 PC4/A4/D4 34 PC3/A3/D3 33 PC2/A2/D2 32 PC1/A1/D1 31 PC0/A0/D0 30 XTAL 29 EXTAL 28 STRB/R/W 27 E 26 STRA/AS 25 MODA/LIR

Figure B-2 48-Pin DIP

A8 48-PIN DIP
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MC68HC11A8

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64 PA1/IC2 63 PA2/IC1 62 PA3/OC5/OC1 61 NC 60 NC 59 PA4/OC4/OC1 58 PA5/OC3/OC1 57 PA6/OC2/OC1 56 PA7/PAI/OC1 55 VDD 54 PD5/SS 53 PD4/SCK 52 PD3/MOSI 51 PD2/MISO 50 PD1/TxD 49 VSS

PA0/IC3 1 NC 2 NC 3 NC 4

PB7/A15 5 PB6/A14 6 PB5/A13 7 PB4/A12 8 PB3/A11 9 PB2/A10 10 PB1/A9 11 PB0/A8 12 PE0/AN0 13 PE4/AN4 14 PE1/AN1 15 PE5/AN5 16
48 NC 47 PD0/RxD 46 IRQ 45 XIRQ 44 NC 43 RESET 42 PC7/A7/D7 41 PC6/A6/D6 40 PC5/A5/D5 39 PC4/A4/D4 38 PC3/A3/D3 37 PC2/A2/D2 36 PC1/A1/D1 35 NC 34 PC0/A0/D0 33 XTAL

PE2/AN2 17 PE6/AN6 18 PE3/AN3 19 PE7/AN7 20

VRL 21 VRH 22 VSS 23 VSS 24 MODB/VSTBY 25 NC 26 MODA/LIR 27 STRA/AS 28

E 29 STRB/R/W 30

EXTAL 31 NC 32

Figure B-3 64-Pin QFP

A8 64-PIN QFP

B.2 Package Dimensions

The latest versions of case outlines 778-02, 767-02, and 840B-01 can be obtained from our website at

TECHNICAL DATA
MECHANICAL DATA AND ORDERING INFORMATION

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MOTOROLA B-3

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Package 52-Pin PLCC
48-Pin DIP 64-Pin QFP
Table B-1 Ordering Information

Temperature 40° to + 85°C 40° to + 85°C 40° to + 85°C 40° to + 85°C 40° to + 105°C 40° to + 125°C 40° to + 85°C 40° to + 85°C 40° to + 105°C 40° to + 125°C 40° to + 85°C 40° to + 105°C 40° to + 125°C

CONFIG

Description No ROM, No EEPROM No ROM, No EEPROM, 3 MHz No ROM No ROM, 3 MHz No ROM No ROM No ROM, COP On No ROM, COP On, 3 MHz No ROM, COP On No ROM, COP On BUFFALO ROM BUFFALO ROM BUFFALO ROM
40° to + 85°C

No ROM, No EEPROM
40° to + 85°C

No ROM, No EEPROM, 3 MHz
40° to + 85°C

No ROM
40° to + 85°C

No ROM, 3 MHz
40° to + 105°C

No ROM
40° to + 125°C

No ROM
40° to + 85°C

No ROM, COP On
40° to + 85°C

No ROM, COP On, 3 MHz
40° to + 105°C

No ROM, COP On
40° to + 125°C

No ROM, COP On
40° to + 85°C

BUFFALO ROM
40° to + 105°C

BUFFALO ROM
40° to + 125°C

BUFFALO ROM
40° to + 85°C

No ROM, No EEPROM
40° to + 85°C

No ROM, No EEPROM, 3 MHz
40° to + 85°C

No ROM
40° to + 85°C

No ROM, 3 MHz
40° to + 105°C

No ROM
40° to + 125°C
MECHANICAL DATA AND ORDERING INFORMATION

MC68HC11A8

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MC 68 HC P 7 11XX B C FN 3 R2

QUALIFICATION LEVEL MC FULLY SPECIFIED AND QUALIFIED XC PILOT PRODUCTION DEVICE PC ENGINEERING SAMPLE

NUMERIC DESIGNATOR OPTIONAL

OPERATING VOLTAGE RANGE HC HCMOS VDD = VDC ±10% L HCMOS VDD = VDC TO VDC

COP OPTION ONLY ON A-SERIES DEVICES NONE COP DISABLED P COP ENABLED

MEMORY TYPE BLANK MASKED ROM OR NO ROM 7 EPROM/OTPROM 8 EEPROM

BASE PART NUMBER
11A8, 11D3, 11E9, 11K4, ETC.

MONITOR MASK NONE BLANK B BUFFALO

TEMPERATURE RANGE NONE 0°C TO 70°C 40°C TO 85°C V 40°C TO 105°C M 40°C TO 125°C

PACKAGE TYPE FN 44/52/68/84-PIN PLCC FS 44/52/68/84-PIN CLCC FU 64/80-PIN QFP FB 44-PIN QFP PV 112-PIN TQFP PU 80/100-PIN TQFP PB 52-PIN TQFP P 40/48-PIN DIP S 48-PIN SDIP

MAXIMUM SPECIFIED CLOCK SPEED 2 MHz 3 MHz 4 MHz

TAPE AND REEL OPTION NONE STANDARD PACKAGING R2 TAPE AND REEL PACKAGING

Figure B-4 M68HC11 P/N Options

HC11 PART NUMBERING

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MECHANICAL DATA AND ORDERING INFORMATION

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MECHANICAL DATA AND ORDERING INFORMATION

MC68HC11A8

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C DEVELOPMENT SUPPORT

C.1 M68HC11EVB Evaluation Board

Refer to the M68HC11EVB Evaluation Board User’s Manual M68HC11EVB/D1 . The Evaluation Board EVB is a low cost tool for debugging and evaluating M68HC11 MCU-based target system equipment. The EVB is designed to operate in either the debugging or evaluation mode of operation.

C.1.1 EVB Features
• A low cost means of debugging user-assembled code and evaluating target systems incorporating M68HC11 MCUs
• One-line assembler/disassembler
• Host computer downloading capability
• M68HC11 MCU-based debugging/evaluating circuitry
• MC68HC24 Port Replacement Unit PRU -based MCU l/O expansion circuitry
• MC6850 Asynchronous Communications Interface Adaptor AClA -based termi-
nal l/O port circuitry
• RS-232C compatible terminal/host computer l/O ports

C.2 M68HC11EVBU Universal Evaluation Board

Refer to M68HC11EVBU Universal Evaluation Board User’s Manual M68HC11EVBU/AD1 . The EVBU is a low cost development tool for debugging and evaluation of MC68HC11A8, E9, 7E9, and 8E2 MCUs. The EVBU was designed along with a monitor/debugging program called BUFFALO Bit User Fast Friendly Aid to Logical Operations . This monitor program is contained in MCU ROM. The debugging/ evaluation operation allows the user to debug user code under control of the BUFFALO monitor program.

C.2.1 EVBU Features
• A low-cost means of debugging user assembled code and evaluating MC68HC11A8, E9, 7E9, and 8E2 MCU devices
• BUFFALO monitor in ROM or PCBUG11 software working through boot mode
• One-line assembler/disassembler
• Program downloading capability
• M68HC11-based debugging/evaluating circuitry
• RS-232C compatible terminal l/O port
• Wire-wrap area for custom interfacing
• Single +5 Vdc input power source requirements

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DEVELOPMENT SUPPORT

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C.3 M68HC11EVM Evaluation Module

Refer to M68HC11EVM Evaluation Module User’s Manual M68HC11EVM/AD7 . The EVM is a tool for designing, debugging, and evaluation of M68HC11 MCU-based target system equipment. By providing MCU timing and l/O circuitry, the EVM simplifies user evaluation of the prototype hardware/software product. The EVM requires a usersupplied power supply and an RS-232C compatible terminal for operation. The EVM evaluates both single-chip and expanded-multiplexed modes of operation. Generating, executing, and debugging target system MCU code is accomplished in either mode.

C.3.1 EVM Features
• Low cost means of evaluating target systems with M68HC11 A- and E-series devices
• Monitor/debugger firmware
• One-line assembler/disassembler
• Host computer download capability
• Dual 64 Kbyte memory maps:
16 Kbyte monitor EPROM 8 Kbyte/16 Kbyte user pseudo-ROM
• EEPROM MCU programmer
• MCU single-chip/expanded-multiplexed mode extension l/O ports
• RS-232C terminal and host computer l/O ports

C.4 MMDS11 Modular Development System

The M68MMDS11 Motorola Modular Development System MMDS11 is an emulator system for developing embedded systems based on an M68HC11 microcontroller unit MCU . The MMDS11 provides a bus state analyzer and real-time memory windows. The unit's integrated development environment includes an editor, an assembler, user interface, and source-level debugging capability. These features significantly reduce the time necessary to develop and debug an embedded control system. The unit's compact size requires a minimum of bench space. The MMDS11 is one component of Motorola's modular approach to MCU-based product development. This modular approach allows easy configuration of the MMDS11 to fit a wide range of requirements. It also reduces development system cost by allowing the user to purchase only the modular components necessary to support the particular MCU device family.

The station module is a metal enclosure that contains a printed circuit board the control board , a test emulator module TEM , and an internal power supply. A power cable, an RS-232 serial cable, two logic clip cables with clips , and a 9- to 25-pin RS232 adapter come with the MMDS11. The system requires an IBM-PC or compatible host computer. Connection to a target system is via a separately purchased M68HC11 emulator module EM and target cable. The EM completes MMDS11 functionality for a particular MCU derivative or MCU family. The many EMs available let the system emulate a variety of different M68HC11 MCUs. Connection to a target system is made with a separately purchased cable with the appropriate connector which connects the EM to the target system. MMDS11 features include:

DEVELOPMENT SUPPORT

MC68HC11A8

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Appendix B Mechanical Data and Ordering Information

Page B-4 to B-6 Case Outlines removed.

Page B-8

Figure B-7 has been replaced.

TECHNICAL DATA

SUMMARY OF CHANGES

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MC68HC11A8

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More datasheets: LA50QS1504 | LA50QS6004 | LA50QS4504 | LA50QS5004 | MC68HC11A1MFNER | MC68HC11A1MFNE | MC68HC11A0CFNE3 | MC68HC11A1CFNE3 | MC68HC11A1CFNE3R | MCP11A1CFNE3R


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Datasheet ID: MCP11A1CFNE3 635491