MC68EC020FG25

MC68EC020FG25 Datasheet

MC68020 MC68EC020

Part	Datasheet
MC68EC020FG25	MC68EC020FG25 (pdf)

Related Parts	Information
MC68EC020AA25R	MC68EC020AA25R
MC68EC020AA25	MC68EC020AA25
MC68EC020AA16	MC68EC020AA16

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MC68020 MC68EC020 MICROPROCESSORS USER’S MANUAL First Edition Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA INC., 1992 The M68020 User’s Manual describes the capabilities, operation, and programming of the MC68020 32-bit, second-generation, enhanced microprocessor and the MC68EC020 32bit, second-generation, enhanced embedded microprocessor. Throughout this manual, “MC68020/EC020” is used when information applies to both the MC68020 and the MC68EC020. “MC68020” and “MC68EC020” are used when information applies only to the MC68020 or MC68EC020, respectively. For detailed information on the MC68020 and MC68EC020 instruction set, refer to M68000PM/AD, M68000 Family Programmer’s Reference Manual. This manual consists of the following sections: Section 1 Introduction Section 2 Processing States Section 3 Signal Description Section 4 On-Chip Cache Memory Section 5 Bus Operation Section 6 Exception Processing Section 7 Coprocessor Interface Description Section 8 Instruction Execution Timing Section 9 Applications Information Section 10 Electrical Characteristics Section 11 Ordering Information and Mechanical Data Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol NOTE In this manual, assert and negate are used to specify forcing a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false. These terms are used independently of the voltage level high or low that they represent. MOTOROLA M68020 USER’S MANUAL 9/29/95 SECTION 1 OVERVIEW Paragraph Number TABLE OF CONTENTS Page Number Section 1 Introduction Features Programming Model Data Types and Addressing Modes Overview Instruction Set Overview Virtual Memory and Virtual Machine Concepts Virtual Memory Virtual Machine Pipelined Architecture Cache Memory Section 2 Processing States Privilege Levels Supervisor Privilege Level User Privilege Level Changing Privilege Level 2-3 Address Space Types Exception Exception Vectors Exception Stack Frame Section 3 Signal Description Signal Index Function Code Signals Address Bus MC68EC020 Data Bus Transfer Size Signals SIZ1, SIZ0 Asynchronous Bus Control Signals Interrupt Control Bus Arbitration Control Signals Bus Exception Control Signals Emulator Support Signal Clock CLK MOTOROLA M68020 USER’S MANUAL 9/29/95 SECTION 1 OVERVIEW TABLE OF CONTENTS Continued Paragraph Number Page Number Power Supply Connections Signal Section 4 On-Chip Cache Memory On-Chip Cache Organization and Operation Cache Reset Cache Control Cache Control Register CACR Cache Address Register CAAR Section 5 Bus Operation Bus Transfer Bus Control Signals Address Bus 5-3 Address Strobe Data 5-3 Data Strobe Data Buffer Enable Bus Cycle Termination Data Transfer Dynamic Bus Sizing Misaligned Effects of Dynamic Bus Sizing and Operand Misalignment 5-20 Address, Size, and Data Bus Relationships Cache Interactions Bus Operation 5-24 Synchronous Operation with DSACK1/DSACK0 5-24 Data Transfer Cycles Read Cycle Write Cycle Read-Modify-Write CPU Space Cycles Interrupt Acknowledge Bus Cycles Interrupt Acknowledge Normally 5-45 Autovector Interrupt Acknowledge Cycle Spurious Interrupt Cycle Breakpoint Acknowledge Cycle Coprocessor Communication Cycles 5-53 Bus Exception Control Bus Errors 5-55 viii M68020 USER’S MANUAL MOTOROLA Section 11 Ordering Information and Mechanical Data Standard Ordering Standard MC68020 Ordering Standard MC68EC020 Ordering Information Pin Assignments and Package Dimensions MC68020 RC and RP Assignment MC68020 RC Dimensions 11-3 MC68020 RP MC68020 FC and FE Assignment 11-5 MC68020 FC Dimensions MC68020 FE Dimensions MC68EC020 RP MC68EC020 RP Dimensions MC68EC020 FG MC68EC020 FG Dimensions Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol MOTOROLA M68020 USER’S MANUAL xiii 9/29/95 SECTION 1 OVERVIEW LIST OF ILLUSTRATIONS Figure Number Page Number 1-1 MC68020/EC020 Block Diagram 1-2 User Programming Model 1-3 Supervisor Programming Model Supplement 1-6 1-4 Status Register SR 1-7 1-5 Instruction Pipe 2-1 General Exception Stack Frame 2-6 3-1 Functional Signal Groups 4-1 MC68020/EC020 On-Chip Cache Organization 4-2 Cache Control Register 4-3 Cache Address Register 4-4 5-1 5-2 5-3 5-4 5-5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 Relationship between External and Internal 5-2 Input Sample Window Internal Operand Representation MC68020/EC020 Interface to Various Port Sizes Long-Word Operand Write to Word Port 5-10 Long-Word Operand Write to Word Port Timing Word Operand Write to Byte Port Example 5-12 Word Operand Write to Byte Port Misaligned Long-Word Operand Write to Word Port Example 5-14 Misaligned Long-Word Operand Write to Word Port Timing............................ 5-15 Misaligned Long-Word Operand Read from Word Port Example 5-16 Misaligned Word Operand Write to Word Port 5-16 Misaligned Word Operand Write to Word Port Timing 5-17 Misaligned Word Operand Read from Word Bus Example 5-18 Misaligned Long-Word Operand Write to Long-Word Port Example 5-18 Misaligned Long-Word Operand Write to Long-Word Port Timing 5-19 Misaligned Long-Word Operand Read from Long-Word Port Example 5-20 Byte Enable Signal Generation for 16- and 32-Bit Ports 5-23 Long-Word Read Cycle Flowchart 5-26 Byte Read Cycle Flowchart Byte and Word Read Port 5-28 Long-Word Port Long-Word and 32-Bit Ports 5-30 M68020 USER’S MANUAL MOTOROLA 9/29/95 SECTION 1 OVERVIEW LIST OF ILLUSTRATIONS Continued Figure Number Page Number 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52 Write Cycle Flowchart Read-Write-Read Port Byte and Word Write Port Long-Word Operand Port Long-Word Operand Read-Modify-Write Cycle Flowchart Byte Read-Modify-Write Port TAS Instruction 5-41 MC68020/EC020 CPU Space Address Encoding Interrupt Acknowledge Cycle Flowchart Interrupt Acknowledge Cycle Autovector Operation Timing Breakpoint Acknowledge Cycle Flowchart Breakpoint Acknowledge Cycle Timing Breakpoint Acknowledge Cycle Timing Exception Signaled Bus Error without DSACK1/DSACK0 Late Bus Error with DSACK1/DSACK0 Late Halt Operation Timing MC68020 Bus Arbitration Flowchart for Single Request MC68020 Bus Arbitration Operation Timing for Single Request MC68020 Bus Arbitration State Diagram MC68020 Bus Arbitration Operation Inactive MC68EC020 Bus Arbitration Flowchart for Single Request 5-71 MC68EC020 Bus Arbitration Operation Timing for Single Request 5-72 MC68EC020 Bus Arbitration State Diagram MC68EC020 Bus Arbitration Operation Inactive 5-75 Interface for Three-Wire to Two-Wire Bus Arbitration Initial Reset Operation Timing RESET Instruction Timing 6-1 Reset Operation Flowchart 6-2 Interrupt Pending Procedure 6-3 Interrupt Recognition Examples 6-4 Assertion of IPEND MC68020 Only 6-5 Interrupt Exception Processing Flowchart 6-6 Breakpoint Instruction Flowchart 6-7 RTE Instruction for Throwaway Four-Word Frame 6-8 Special Status Word Format 7-1 F-Line Coprocessor Instruction Operation 7-2 Asynchronous Non-DMA M68000 Coprocessor Interface Signal Usage 7-5 7-3 MC68020/EC020 CPU Space Address Encodings MOTOROLA M68020 USER’S MANUAL 9/29/95 SECTION 1 OVERVIEW LIST OF ILLUSTRATIONS Continued Figure Number Page Number 7-4 7-5 7-6 7-7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37 7-38 7-39 7-40 7-41 7-42 7-43 7-44 Coprocessor Address Map in MC68020/EC020 CPU Space 7-7 Coprocessor Interface Register Set Map Coprocessor General Instruction Format cpGEN Coprocessor Interface Protocol for General Category Instructions.................. 7-10 Coprocessor Interface Protocol for Conditional Category Instructions 7-11 Branch on Coprocessor Condition Instruction Format cpBcc.W 7-12 Branch on Coprocessor Condition Instruction Format cpBcc.L 7-12 Set on Coprocessor Condition Instruction Format cpScc 7-13 Test Coprocessor Condition, Decrement, and Branch Instruction Format Trap on Coprocessor Condition Instruction Format cpTRAPcc 7-15 Coprocessor State Frame Format in Memory Coprocessor Context Save Instruction Format cpSAVE 7-20 Coprocessor Context Save Instruction Protocol 7-21 Coprocessor Context Restore Instruction Format cpRESTORE 7-22 Coprocessor Context Restore Instruction Protocol Control CIR Format Condition CIR Format Operand Alignment for Operand CIR Accesses 7-26 Coprocessor Response Primitive Format 7-28 Busy Primitive Format Null Primitive Supervisor Check Primitive Transfer Operation Word Primitive Format Transfer from Instruction Stream Primitive Format Evaluate and Transfer Effective Address Primitive Format.............................. 7-35 Evaluate Effective Address and Transfer Data Primitive Format 7-35 Write to Previously Evaluated Effective Address Primitive Format 7-37 Take Address and Transfer Data Primitive Format Transfer to/from Top of Stack Primitive Format Transfer Single Main Processor Register Primitive Format 7-40 Transfer Main Processor Control Register Primitive Format Transfer Multiple Main Processor Registers Primitive Format 7-42 Register Select Mask Format Transfer Multiple Coprocessor Registers Primitive Format.............................. 7-43 Operand Format in Memory for Transfer to Transfer Status Register and ScanPC Primitive Format.................................. 7-44 Take Preinstruction Exception Primitive Format 7-45 MC68020/EC020 Preinstruction Stack Frame 7-46 Take Midinstruction Exception Primitive Format MC68020/EC020 Midinstruction Stack Frame Take Postinstruction Exception Primitive M68020 USER’S MANUAL MOTOROLA 9/29/95 The MC68EC020 is an economical high-performance embedded microprocessor based on the MC68020 and has been designed specifically to suit the needs of the embedded microprocessor market. The major differences in the MC68EC020 and the MC68020 are that the MC68EC020 has a 24-bit address bus and does not implement the following signals ECS, OCS, DBEN, IPEND, and BGACK. Also, the available packages and frequencies differ for the MC68020 and MC68EC020 see Section 11 Ordering Information and Mechanical Data. Unless otherwise stated, information in this manual applies to both the MC68020 and the MC68EC020. MOTOROLA M68020 USER’S MANUAL The main features of the MC68020/EC020 are as follows • Object-Code Compatible with Earlier M68000 Microprocessors • Addressing Mode Extensions for Enhanced Support of High-Level Languages • New Bit Field Data Type Accelerates Bit-Oriented Video Graphics • An On-Chip Instruction Cache for Faster Instruction Execution • Coprocessor Interface to Companion 32-Bit MC68881 and MC68882 Floating-Point Coprocessors and the MC68851 Paged Memory Management Unit • Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple Instructions To Be Executed Concurrently • High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32 Bits • Dynamic Bus Sizing Efficiently Supports 8-/16-/32-Bit Memories and Peripherals • Full Support of Virtual Memory and Virtual Machine • Sixteen 32-Bit General-Purpose Data and Address Registers • Two 32-Bit Supervisor Stack Pointers and Five Special-Purpose Control Registers • Eighteen Addressing Modes and Seven Data Types • 4-Gbyte Direct Addressing Range for the MC68020 • 16-Mbyte Direct Addressing Range for the MC68EC020 • Selection of Processor Speeds for the MC68020 20, 25, and MHz • Selection of Processor Speeds for the MCEC68020 and 25 MHz A block diagram of the MC68020/EC020 is shown in Figure M68020 USER’S MANUAL MOTOROLA SEQUENCER AND CONTROL CONTROL STORE INSTRUCTION PIPE STAGE CACHE HOLDING REGISTER CAHR CONTROL LOGIC INSTRUCTION CACHE ADDRESS BUS * 32-BIT INSTRUCTION ADDRESS BUS EXECUTION UNIT INTERNAL DATA BUS DATA PADS 32-BIT DATA BUS ADDRESS PADS PROGRAM COUNTER SECTION ADDRESS SECTION DATA SECTION SIZE MULTIPLEXER ADDRESS BUS BUS CONTROLLER WRITE PENDING BUFFER PREFETCH PENDING BUFFER MICROBUS CONTROL LOGIC MISALIGNMENT MULTIPLEXER BUS CONTROL SIGNALS * 24-Bit for MC68EC020 Figure MC68020/EC020 Block Diagram MOTOROLA M68020 USER’S MANUAL PROGRAMMING MODEL The programming model of the MC68020/EC020 consists of two groups of registers, the user model and the supervisor model, that correspond to the user and supervisor privilege levels, respectively. User programs executing at the user privilege level use the registers of the user model. System software executing at the supervisor level uses the control registers of the supervisor level to perform supervisor functions. As shown in the programming models see Figures 1-2 and 1-3 , the MC68020/EC020 has 16 32-bit general-purpose registers, a 32-bit PC two 32-bit SSPs, a 16-bit SR, a 32-bit VBR, two 3-bit alternate function code registers, and two 32-bit cache handling address and control registers. The user programming model remains unchanged from earlier M68000 family microprocessors. The supervisor programming model supplements the user programming model and is used exclusively by MC68020/EC020 system programmers who utilize the supervisor privilege level to implement sensitive operating system functions. The supervisor programming model contains all the controls to access and enable the special features of the MC68020/EC020. All application software, written to run at the nonprivileged user level, migrates to the MC68020/EC020 from any M68000 platform without modification. The MC68020/EC020 requires connection to a VCC power supply, positive with respect to ground. The VCC connections are grouped to supply adequate current for the various sections of the processor. The ground connections are similarly grouped. Section 11 Ordering Information and Mechanical Data describes the groupings of VCC and ground connections, and Section 9 Applications Information describes a typical power supply interface. MOTOROLA M68020 USER’S MANUAL SIGNAL SUMMARY Table 3-2 provides a summary of the characteristics of the signals discussed in this section. Signal names preceded by an asterisk * are implemented in the MC68020 and not implemented in the MC68EC020. Table Signal Summary Signal Function Signal Name Input/Output Active State Function Codes Output High Address Bus MC68020 MC68EC020 Output High Data Bus Input/Output High Transfer Size SIZ1, SIZ0 Output High Operand Cycle Start Output External Cycle Start Output Read/Write Output High/Low Read-Modify-Write Cycle Output Address Strobe Output Data Strobe Output *Data Buffer Enable DBEN Output Data Transfer and Size Acknowledge DSACK1, DSACK0 Input To reduce the amount of noise in the power supply connected to the MC68020/EC020 and to provide for the instantaneous current requirements, common capacitive decoupling techniques should be observed. While there is no recommended layout for this capacitive decoupling, it is essential that the inductance and distance between these devices and the MC68020/EC020 be minimized to provide sufficiently fast response time to satisfy momentary current demands and to maintain a constant supply voltage. It is suggested that high-frequency, high-quality capacitors be placed as close to the MC68020/EC020 as possible. Table 9-2 lists the VCC and GND pin assignments for the MC68EC020 PPGA RP suffix package. Table 9-3 lists the VCC and GND pin assignments for the MC68EC020 PQFP FG suffix package. Refer to Section 11 Ordering Information and Mechanical Data for the VCC and GND pin assignments for the MC68020 packages. When assigning capacitors to the VCC and GND pins, the noisier pins address and data buses should be heavily decoupled from the internal logic pins. Typical decoupling practices include a high-frequency, high-quality capacitor to decouple every device on the printed circuit board however, due to the power requirements and drive capability of the MC68020/EC020, each VCC pin should be decoupled with an individual capacitor. Motorola recommends using a capacitor in the range of µF to µF on each VCC pin on each device to provide filtering for most frequencies prevalent in a digital system. In addition to the individual decoupling, several bulk decoupling capacitors should be placed onto the printed circuit board with typical values in the range of 33 µF to 330 µF. When power and ground planes are used with an adequate number of high-frequency, highquality capacitors, the system noise will be reduced to the required levels, and the MC68020/EC020 will function properly. Similar decoupling techniques should also be observed for other VLSI devices in the system. In addition to the capacitive decoupling of the power supply, care must be taken to ensure a low-impedance connection between all MC68020/EC020 VCC and GND pins and the system power supply. A solid power supply connection from the power and ground planes to the MC68020/EC020 VCC and GND pins, respectively, will meet this requirement. Failure to provide connections of sufficient quality between the MC68020/EC020 power pins and the system power supplies will result in increased assertion delays for external signals, decreased voltage noise margins, increased system noise, and possible errors in MC68020/EC020 internal logic. MOTOROLA M68020 USER’S MANUAL Table VCC and GND Pin MC68EC020 PPGA RP Suffix Pin Group Address Bus Data Bus Internal Logic Clock VCC B7, C7 K12, M9, N9 D1, D2, E12, E13 GND A1, A7, C8, D13 J13, L8, M1, M8 F11, F12, J1, J2 Table VCC and GND Pin MC68EC020 PQFP FG Suffix Pin Group Address Bus Data Bus Internal Logic Clock VCC 90 44, 57 7, 8, 70, 71 GND 72, 89, 100 26, 43, 58, 59 3, 20, 21, 68, 69 CLOCK DRIVER The MC68020/EC020 is designed to sustain high performance while using low-cost memory subsystems. The MC68020/EC020 requires a stable clock source that is free of ringing and ground bounce, has sufficient rise and fall times, and meets the minimum and maximum high and low cycle times. The individual system may require additional clocks for peripherals with a minimum amount of clock skew. Two possible clock solutions are provided with the MC88916 and MC74F803. Many other clock solutions can be used. Some crystal clock drivers are capable of driving the MC68020/EC020 directly. For slower speed designs, a simple 74F74 flip-flop meets the clocking needs of the MC68020/EC020. Coupled with the MC88916 or MC74F803 clock generation and distribution circuit, the MC68020/EC020 provides simple interface to lower speed memory subsystems. The MC88916 see Figure 9-7 and MC74F803 see Figure 9-8 generate the clock signals required to minimize the skew between different clocks to multiple devices such as coprocessors, synchronous state machines, DRAM controllers, and memory subsystems. The MC88916 clock driver can be used in doubling and synchronizing a low-frequency clock source. The MC74F803 will provide a controlled skew output for clocking other peripherals. 9-10 M68020 USER’S MANUAL MOTOROLA 12.5-MHz OSCILLATOR CONTROLLER CLOCK 25 MHz MC88916 CLOCK 2 50 MHz BUS CLOCKS 25 MHz CLOCK 25 MHz MC68020/EC020 25 MHz Figure High-Resolution Clock Controller 50-MHz OSCILLATOR MC74F803 CONTROLLER CLOCK 25 MHz MC68020/EC020 25 MHz CLOCK 25 MHz BUS CLOCKS 25 MHz Figure Alternate Clock Solution MEMORY INTERFACE The MC68020/EC020 is capable of running an external bus cycle in a minimum of three clocks refer to Section 5 Bus Operation . The MC68020/EC020 runs an asynchronous bus cycle, terminated by the DSACK1/DSACK0 signals, and has a minimum duration of three controller clock periods in which up to four bytes 32 bits are transferred. During read operations, the MC68020/EC020 latches data on the last falling clock edge of the bus cycle, one-half clock before the bus cycle ends. Latching data here, instead of the next rising clock edge, helps to avoid data bus contention with the next bus cycle and allows the MC68020/EC020 to receive the data into its execution unit sooner for a net performance increase. Write operations also use this data bus timing to allow data hold times from the negating strobes and to avoid any bus contention with the following bus cycle. This MC68020/EC020 characteristic allows the system to be designed with a minimum of bus buffers and latches. One benefit of the MC68020/EC020 on-chip instruction cache is that the effect of external wait states on performance is lessened because the caches are always accessed in fewer than “no wait states,” regardless of the external memory configuration. MOTOROLA M68020 USER’S MANUAL 9-11 SECTION 11 ORDERING INFORMATION AND MECHANICAL DATA This section contains the pin assignments and package dimensions of the MC68020 and the MC68EC020. In addition, detailed information is provided to be used as a guide when ordering. STANDARD ORDERING INFORMATION Standard MC68020 Ordering Information Package Type Ceramic Pin Grid Array RC Suffix Plastic Quad Flat Pack FC Suffix Plastic Pin Grid Array RP Suffix Ceramic Quad Flat Pack FE Suffix Frequency MHz Temperature °C 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 0 to 70 Order Number MC68020RC16 MC68020RC20 MC68020RC25 MC68020RC33 MC68020FC16 MC68020FC20 MC68020FC25 MC68020RP16 MC68020RP20 MC68020RP25 MC68020FE16 MC68020FE20 MC68020FE25 MC68020FE33 Standard MC68EC020 Ordering Information Package Type Plastic Pin Grid Array RP Suffix Plastic Quad Flat Pack FG Suffix Frequency MHz Temperature °C 0 to 70 0 to 70 0 to 70 0 to 70 Order Number MC68EC020RP16 MC68EC020RP25 MC68EC020FG16 MC68EC020FG25 MOTOROLA MC68838 USER’S MANUAL 13-1 PIN ASSIGNMENTS AND PACKAGE DIMENSIONS MC68020 RC and RP Assignment N D31 D28 D25 D22 D20 D17 GND VCC D14 D12 D9 D8 VCC M DS D29 D26 D24 D21 D18 D16 VCC D13 D10 D6 D5 D4 L AS R/W D30 D27 D23 D19 GND D15 D11 D7 GND D3 D2 GND HALT GND D1 D0 DSACK1 BERR GND IPL0 IPL1 CDIS AVEC DSACK0 IPL2 GND G ECS SIZ1 DBEN MC68020 VCC GND VCC SIZ0 FC2 FC1 GND IPEND E FC0 RMC VCC A2 OCS VCC C A4 A3 RESET CLK GND A0 A29 A25 A21 A17 A16 A12 A9 A7 A5 B GND BG BR A30 A27 A24 A20 A18 GND A15 A13 A10 A6 A BGACK A1 A31 A28 A26 A23 A22 A19 VCC GND A14 A11 A8 1 2 3 4 5 6 7 8 9 10 11 12 13 The VCC and GND pins are separated into four groups to provide individual power supply connections for the address bus buffers, data bus buffers, and all other output buffers and internal logic. It is recommended that all pins be connected to power and ground as indicated. Group Address Bus Data Bus Logic Clock VCC A9, D3 M8, N8, N13 D1, D2, E3, G11, G13 GND A10, B9, C3, F12 L7, L11, N7, K3 G12, H13, J3, K1 OCS Signal, 3-4, 5-3 Ordering Information MC68020, 11-1 MC68EC020, 11-1 Overlap, 8-3 Package Dimensions MC68020 FC Suffix, 11-6 MC68020 FE Suffix, 11-7 MC68020 RC Suffix, 11-3 MC68020 RP Suffix, 11-4 MC68EC020 FG Suffix, 11-11 MC68EC020 RP Suffix, 11-9 Pin Assignment MC68020 FC Suffix, 11-5 MC68020 FE Suffix, 11-5 MC68020 RC Suffix, 11-2 MC68020 RP Suffix, 11-2 MC68EC020 FG Suffix, 11-10 MC68EC020 RP Suffix, 11-8 Port Size, 5-1, 5-5, 5-21, 9-5 Power Supply, 3-7, 9-9 Primitive, 7-4, 7-27 Busy Response Primitive, 7-30 CA Bit, 7-29 DR Bit, 7-29 Evaluate and Transfer Effective Address Primitive, 7-35 Evaluate Effective Address and Transfer Data Primitive, 7-35 Format, 7-28 Null Coprocessor Response Primitive, 7-31 PC Bit, 7-29 Supervisor Check Primitive, 7-33 Take Address and Transfer Data Primitive, 7-39 Take Midinstruction Exception Primitive, 7-47 Take Postinstruction Exception Primitive, 7-48 Take Preinstruction Exception Primitive, 7-45 Transfer from Instruction Stream Primitive, 7-34 Transfer Main Processor Control Register Primitive, 7-41 Transfer Multiple Coprocessor Registers Primitive, 7-42 Transfer Multiple Main Processor Registers Primitive, 7-42 Transfer Operation Word Primitive, 7-33 Transfer Single Main Processor Register Primitive, 7-40 INDEX-4 M68020 USER’S MANUAL MOTOROLA Transfer Status Register and the scanPC Primitive, 7-44 Transfer to/from Top of Stack Primitive, 7-40 Write to Previously Evaluated Effective Address Primitive, 7-37 Privilege Level, 2-2 Changing, 2-3 Supervisor Level, 1-4, 2-2 User Level, 1-4, 2-2 Privilege Violation Exception, 6-7, 6-8 Processing States, 2-1 Program Counter PC , 1-4 Programming Model, 1-4, 7-1, 7-2 Read Cycle, 5-3, 5-4, 5-8, 5-14, 5-16, 5-18, 5-22, 5-26 Byte Read Cycle, 5-26 Long-Word Read Cycle, 5-26, 8-2 Timing, 5-26 Read-Modify-Write Cycle, 5-3, 5-39, 5-42 Timing, 5-39 Registers Address Registers, 1-4 CAAR, 1-7, 4-3, 4-4 CACR, 1-7, 4-2, 4-3 Data Registers, 1-4 DFC, 1-7 Internal Cache Holding Register, 5-21 Program Counter PC , 1-4 SFC, 1-7 SR, 1-7, 4-1 VBR, 1-7 Reset, 4-3 Flowchart, 6-4 Reset Exception, 6-4 RESET Instruction, 7-58 RESET Signal, 3-6, 5-76, 6-4 Reset Exception, 6-4 RESET Instruction, 5-76 RESET Signal, 3-6, 5-76, 6-4 Retry, 5-56 RMC Signal, 3-4, 5-3, 5-39 RTE Instruction, 6-19, 6-24 RTM Instruction, 9-14, 9-16, 9-19 R/W Signal, 3-4, 5-2, 5-3, 9-5 S-bit SR , 1-7, 2-2, 2-3 Save and Restore Operations, 8-40 scanPC, 7-28 Sequencer, 8-2, 8-5 Shift/Rotate Instructions, 8-34 Signal s , 3-8 A1,A0, 5-2, 5-7, 5-9, 5-21, 9-5 7-6 7-6 4-1, 5-3 Address Bus, 3-2, 5-3 AS, 3-4, 5-2, 5-3 AVEC, 3-5, 5-4, 5-48, 5-53 BERR, 3-7, 5-4, 5-25, 5-53, 5-55, 6-4 BG, 3-6, 5-63, 5-66, 5-70, 5-71 BGACK, 3-6, 5-62, 5-63, 5-66 BR, 3-6, 5-63, 5-66, 5-70 Byte Select Control Signals, 9-5 CDIS, 3-7, 4-3 CLK, 3-7 3-2, 5-3 DBEN, 3-5, 5-4 DS, 3-4, 5-4, 5-21 DSACK1, DSACK0, 3-5, 5-4, 5-5, 5-24, 5-46, 5-53, 9-5 ECS, 3-4, 5-3 2-4, 3-2, 5-2, 5-3, 5-44, 7-6 Functional Groups, 3-1 HALT, 3-7, 5-4, 5-25, 5-53, 5-60 Input Signal, 5-2 Internal Signal, 5-2 IPEND, 3-5, 6-14 3-5, 6-11 OCS, 3-4, 5-3 RESET, 3-6, 5-76, 6-4 RMC, 3-4, 5-3, 5-39 R/W, 3-4, 5-2, 5-3, 9-5 SIZ1, SIZ0, 3-2, 5-2, 5-3, 5-7, 5-9, 5-21, 9-5 Single-Operand Instruction, 8-33 SIZ1, SIZ0 Signals, 3-2, 5-2, 5-3, 5-7, 5-9, 5-21, 9-5 Source Function Code Register SFC , 1-7 Special-Purpose MOVE Instruction, 8-29 Special Status Word SSW , 6-21 Spurious Interrupt, 5-48 MOTOROLA M68020 USER’S MANUAL INDEX- 5 Stack Frame Midinstruction, 7-47 Postinstruction, 7-48 Preinstruction, 7-46 Status Register SR , 1-7, 4-1, 5-45, 6-1 STOP Instruction, 6-10 Supervisor Privilege Level, 1-4, 2-2 Supervisor Stack Pointer SSP , 1-4, 2-2 Synchronous Cycles, 5-24 T1, T0 Bits SR , 1-7, 6-9 TAS Instruction, 5-39 Thermal Characteristics, 10-1 MC68020, 10-2 MC68020 CQFP Package, 10-2 MC68EC020, 10-4 MC68EC020 PQFP Package, 10-4 Thermal Resistance, 10-2, 10-4 Timing, 5-26, 5-33 Trace Exception, 6-9 Trace Modes, 1-7 Tracing, 6-9 Transfer, 5-10, 5-14, 5-25 Bus Transfer, 5-1 Direction, 5-3 Misaligned, 5-1, 5-5 Operand Transfer, 5-1, 5-5 Trap Exception, 6-6 Unimplemented Instruction F-Line Opcode Exception, 6-7 User Privilege Level, 1-4, 2-2 User Stack Pointer USP , 1-4, 2-2 VCC Connections, 3-7, 9-9 Vector Base Register VBR , 1-7, 2-5, 6-2 Virtual Machine, 1-12 Virtual Memory, 1-10

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MC68020 MC68EC020

MICROPROCESSORS USER’S MANUAL

First Edition

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

MOTOROLA INC., 1992

The M68020 User’s Manual describes the capabilities, operation, and programming of the MC68020 32-bit, second-generation, enhanced microprocessor and the MC68EC020 32bit, second-generation, enhanced embedded microprocessor.

Throughout this manual, “MC68020/EC020” is used when information applies to both the MC68020 and the MC68EC020. “MC68020” and “MC68EC020” are used when information applies only to the MC68020 or MC68EC020, respectively.

For detailed information on the MC68020 and MC68EC020 instruction set, refer to M68000PM/AD, M68000 Family Programmer’s Reference Manual.

This manual consists of the following sections:
Section 1 Introduction Section 2 Processing States Section 3 Signal Description Section 4 On-Chip Cache Memory Section 5 Bus Operation Section 6 Exception Processing Section 7 Coprocessor Interface Description Section 8 Instruction Execution Timing Section 9 Applications Information Section 10 Electrical Characteristics Section 11 Ordering Information and Mechanical Data Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire

Bus Arbitration Protocol

NOTE

In this manual, assert and negate are used to specify forcing a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false. These terms are used independently of the voltage level high or low that they represent.

MOTOROLA

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SECTION 1 OVERVIEW

Paragraph Number

TABLE OF CONTENTS

Page Number

Section 1 Introduction

Features Programming Model Data Types and Addressing Modes Overview Instruction Set Overview Virtual Memory and Virtual Machine Concepts

Virtual Memory Virtual Machine Pipelined Architecture Cache Memory

Section 2 Processing States

Privilege Levels Supervisor Privilege Level User Privilege Level Changing Privilege Level 2-3

Address Space Types Exception

Exception Vectors Exception Stack Frame

Section 3 Signal Description

Signal Index Function Code Signals Address Bus MC68EC020 Data Bus Transfer Size Signals SIZ1, SIZ0 Asynchronous Bus Control Signals Interrupt Control Bus Arbitration Control Signals Bus Exception Control Signals Emulator Support Signal Clock CLK

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SECTION 1 OVERVIEW

TABLE OF CONTENTS Continued

Paragraph Number

Page Number

Power Supply Connections

Signal

Section 4 On-Chip Cache Memory

On-Chip Cache Organization and Operation Cache Reset Cache Control

Cache Control Register CACR Cache Address Register CAAR

Section 5 Bus Operation

Bus Transfer Bus Control Signals Address Bus 5-3 Address Strobe Data 5-3 Data Strobe Data Buffer Enable Bus Cycle Termination

Data Transfer Dynamic Bus Sizing Misaligned Effects of Dynamic Bus Sizing and Operand Misalignment 5-20 Address, Size, and Data Bus Relationships Cache Interactions Bus Operation 5-24 Synchronous Operation with DSACK1/DSACK0 5-24

Data Transfer Cycles Read Cycle Write Cycle Read-Modify-Write

CPU Space Cycles Interrupt Acknowledge Bus Cycles Interrupt Acknowledge Normally 5-45 Autovector Interrupt Acknowledge Cycle Spurious Interrupt Cycle Breakpoint Acknowledge Cycle Coprocessor Communication Cycles 5-53

Bus Exception Control Bus Errors 5-55
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Section 11 Ordering Information and Mechanical Data
Standard Ordering Standard MC68020 Ordering Standard MC68EC020 Ordering Information

Pin Assignments and Package Dimensions MC68020 RC and RP Assignment MC68020 RC Dimensions 11-3 MC68020 RP MC68020 FC and FE Assignment 11-5 MC68020 FC Dimensions MC68020 FE Dimensions MC68EC020 RP MC68EC020 RP Dimensions MC68EC020 FG MC68EC020 FG Dimensions

Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol

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SECTION 1 OVERVIEW

LIST OF ILLUSTRATIONS

Figure Number

Page Number
1-1 MC68020/EC020 Block Diagram 1-2 User Programming Model 1-3 Supervisor Programming Model Supplement 1-6 1-4 Status Register SR 1-7 1-5 Instruction Pipe
2-1 General Exception Stack Frame 2-6
3-1 Functional Signal Groups
4-1 MC68020/EC020 On-Chip Cache Organization 4-2 Cache Control Register 4-3 Cache Address Register 4-4
5-1 5-2 5-3 5-4 5-5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23

Relationship between External and Internal 5-2 Input Sample Window Internal Operand Representation MC68020/EC020 Interface to Various Port Sizes Long-Word Operand Write to Word Port 5-10 Long-Word Operand Write to Word Port Timing Word Operand Write to Byte Port Example 5-12 Word Operand Write to Byte Port Misaligned Long-Word Operand Write to Word Port Example 5-14 Misaligned Long-Word Operand Write to Word Port Timing............................ 5-15 Misaligned Long-Word Operand Read from Word Port Example 5-16 Misaligned Word Operand Write to Word Port 5-16 Misaligned Word Operand Write to Word Port Timing 5-17 Misaligned Word Operand Read from Word Bus Example 5-18 Misaligned Long-Word Operand Write to Long-Word Port Example 5-18 Misaligned Long-Word Operand Write to Long-Word Port Timing 5-19 Misaligned Long-Word Operand Read from Long-Word Port Example 5-20 Byte Enable Signal Generation for 16- and 32-Bit Ports 5-23 Long-Word Read Cycle Flowchart 5-26 Byte Read Cycle Flowchart Byte and Word Read Port 5-28 Long-Word Port Long-Word and 32-Bit Ports 5-30

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SECTION 1 OVERVIEW

LIST OF ILLUSTRATIONS Continued

Figure Number

Page Number
5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52

Write Cycle Flowchart Read-Write-Read Port Byte and Word Write Port Long-Word Operand Port Long-Word Operand Read-Modify-Write Cycle Flowchart Byte Read-Modify-Write Port TAS Instruction 5-41 MC68020/EC020 CPU Space Address Encoding Interrupt Acknowledge Cycle Flowchart Interrupt Acknowledge Cycle Autovector Operation Timing Breakpoint Acknowledge Cycle Flowchart Breakpoint Acknowledge Cycle Timing Breakpoint Acknowledge Cycle Timing Exception Signaled Bus Error without DSACK1/DSACK0 Late Bus Error with DSACK1/DSACK0 Late Halt Operation Timing MC68020 Bus Arbitration Flowchart for Single Request MC68020 Bus Arbitration Operation Timing for Single Request MC68020 Bus Arbitration State Diagram MC68020 Bus Arbitration Operation Inactive MC68EC020 Bus Arbitration Flowchart for Single Request 5-71 MC68EC020 Bus Arbitration Operation Timing for Single Request 5-72 MC68EC020 Bus Arbitration State Diagram MC68EC020 Bus Arbitration Operation Inactive 5-75 Interface for Three-Wire to Two-Wire Bus Arbitration Initial Reset Operation Timing RESET Instruction Timing
6-1 Reset Operation Flowchart 6-2 Interrupt Pending Procedure 6-3 Interrupt Recognition Examples 6-4 Assertion of IPEND MC68020 Only 6-5 Interrupt Exception Processing Flowchart 6-6 Breakpoint Instruction Flowchart 6-7 RTE Instruction for Throwaway Four-Word Frame 6-8 Special Status Word Format
7-1 F-Line Coprocessor Instruction Operation 7-2 Asynchronous Non-DMA M68000 Coprocessor Interface Signal Usage 7-5 7-3 MC68020/EC020 CPU Space Address Encodings

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SECTION 1 OVERVIEW

LIST OF ILLUSTRATIONS Continued

Figure Number

Page Number
7-4 7-5 7-6 7-7-8 7-9 7-10 7-11 7-12
7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37 7-38 7-39 7-40 7-41 7-42 7-43 7-44

Coprocessor Address Map in MC68020/EC020 CPU Space 7-7 Coprocessor Interface Register Set Map Coprocessor General Instruction Format cpGEN Coprocessor Interface Protocol for General Category Instructions.................. 7-10 Coprocessor Interface Protocol for Conditional Category Instructions 7-11 Branch on Coprocessor Condition Instruction Format cpBcc.W 7-12 Branch on Coprocessor Condition Instruction Format cpBcc.L 7-12 Set on Coprocessor Condition Instruction Format cpScc 7-13 Test Coprocessor Condition, Decrement, and Branch Instruction Format Trap on Coprocessor Condition Instruction Format cpTRAPcc 7-15 Coprocessor State Frame Format in Memory Coprocessor Context Save Instruction Format cpSAVE 7-20 Coprocessor Context Save Instruction Protocol 7-21 Coprocessor Context Restore Instruction Format cpRESTORE 7-22 Coprocessor Context Restore Instruction Protocol Control CIR Format Condition CIR Format Operand Alignment for Operand CIR Accesses 7-26 Coprocessor Response Primitive Format 7-28 Busy Primitive Format Null Primitive Supervisor Check Primitive Transfer Operation Word Primitive Format Transfer from Instruction Stream Primitive Format Evaluate and Transfer Effective Address Primitive Format.............................. 7-35 Evaluate Effective Address and Transfer Data Primitive Format 7-35 Write to Previously Evaluated Effective Address Primitive Format 7-37 Take Address and Transfer Data Primitive Format Transfer to/from Top of Stack Primitive Format Transfer Single Main Processor Register Primitive Format 7-40 Transfer Main Processor Control Register Primitive Format Transfer Multiple Main Processor Registers Primitive Format 7-42 Register Select Mask Format Transfer Multiple Coprocessor Registers Primitive Format.............................. 7-43 Operand Format in Memory for Transfer to Transfer Status Register and ScanPC Primitive Format.................................. 7-44 Take Preinstruction Exception Primitive Format 7-45 MC68020/EC020 Preinstruction Stack Frame 7-46 Take Midinstruction Exception Primitive Format MC68020/EC020 Midinstruction Stack Frame Take Postinstruction Exception Primitive

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The MC68EC020 is an economical high-performance embedded microprocessor based on the MC68020 and has been designed specifically to suit the needs of the embedded microprocessor market. The major differences in the MC68EC020 and the MC68020 are that the MC68EC020 has a 24-bit address bus and does not implement the following signals ECS, OCS, DBEN, IPEND, and BGACK. Also, the available packages and frequencies differ for the MC68020 and MC68EC020 see Section 11 Ordering Information and Mechanical Data. Unless otherwise stated, information in this manual applies to both the MC68020 and the MC68EC020.

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M68020 USER’S MANUAL

The main features of the MC68020/EC020 are as follows
• Object-Code Compatible with Earlier M68000 Microprocessors
• Addressing Mode Extensions for Enhanced Support of High-Level Languages
• New Bit Field Data Type Accelerates Bit-Oriented Video Graphics
• An On-Chip Instruction Cache for Faster Instruction Execution
• Coprocessor Interface to Companion 32-Bit MC68881 and MC68882 Floating-Point Coprocessors and the MC68851 Paged Memory Management Unit
• Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple Instructions To Be Executed Concurrently
• High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32 Bits
• Dynamic Bus Sizing Efficiently Supports 8-/16-/32-Bit Memories and Peripherals
• Full Support of Virtual Memory and Virtual Machine
• Sixteen 32-Bit General-Purpose Data and Address Registers
• Two 32-Bit Supervisor Stack Pointers and Five Special-Purpose Control Registers
• Eighteen Addressing Modes and Seven Data Types
• 4-Gbyte Direct Addressing Range for the MC68020
• 16-Mbyte Direct Addressing Range for the MC68EC020
• Selection of Processor Speeds for the MC68020 20, 25, and MHz
• Selection of Processor Speeds for the MCEC68020 and 25 MHz

A block diagram of the MC68020/EC020 is shown in Figure

M68020 USER’S MANUAL

MOTOROLA

SEQUENCER AND CONTROL

CONTROL STORE

INSTRUCTION PIPE

STAGE

CACHE HOLDING REGISTER CAHR

CONTROL LOGIC

INSTRUCTION CACHE

ADDRESS BUS
* 32-BIT

INSTRUCTION ADDRESS BUS

EXECUTION UNIT

INTERNAL DATA BUS

DATA PADS
32-BIT DATA BUS

ADDRESS PADS

PROGRAM COUNTER SECTION

ADDRESS SECTION

DATA SECTION

SIZE MULTIPLEXER

ADDRESS BUS

BUS CONTROLLER

WRITE PENDING BUFFER

PREFETCH PENDING BUFFER

MICROBUS CONTROL LOGIC

MISALIGNMENT MULTIPLEXER

BUS CONTROL SIGNALS
* 24-Bit for MC68EC020

Figure MC68020/EC020 Block Diagram

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M68020 USER’S MANUAL

PROGRAMMING MODEL

The programming model of the MC68020/EC020 consists of two groups of registers, the user model and the supervisor model, that correspond to the user and supervisor privilege levels, respectively. User programs executing at the user privilege level use the registers of the user model. System software executing at the supervisor level uses the control registers of the supervisor level to perform supervisor functions.

As shown in the programming models see Figures 1-2 and 1-3 , the MC68020/EC020 has 16 32-bit general-purpose registers, a 32-bit PC two 32-bit SSPs, a 16-bit SR, a 32-bit VBR, two 3-bit alternate function code registers, and two 32-bit cache handling address and control registers.

The user programming model remains unchanged from earlier M68000 family microprocessors. The supervisor programming model supplements the user programming model and is used exclusively by MC68020/EC020 system programmers who utilize the supervisor privilege level to implement sensitive operating system functions. The supervisor programming model contains all the controls to access and enable the special features of the MC68020/EC020. All application software, written to run at the nonprivileged user level, migrates to the MC68020/EC020 from any M68000 platform without modification.
The MC68020/EC020 requires connection to a VCC power supply, positive with respect to ground. The VCC connections are grouped to supply adequate current for the various sections of the processor. The ground connections are similarly grouped. Section 11 Ordering Information and Mechanical Data describes the groupings of VCC and ground connections, and Section 9 Applications Information describes a typical power supply interface.

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M68020 USER’S MANUAL

SIGNAL SUMMARY

Table 3-2 provides a summary of the characteristics of the signals discussed in this section. Signal names preceded by an asterisk * are implemented in the MC68020 and not implemented in the MC68EC020.

Table Signal Summary

Signal Function

Signal Name

Input/Output Active State

Function Codes

Output

High

Address Bus MC68020 MC68EC020

Output

High

Data Bus

Input/Output

High

Transfer Size

SIZ1, SIZ0

Output

High
*Operand Cycle Start

Output
*External Cycle Start

Output

Read/Write

Output

High/Low

Read-Modify-Write Cycle

Output

Address Strobe

Output

Data Strobe

Output
*Data Buffer Enable

DBEN

Output

Data Transfer and Size Acknowledge

DSACK1, DSACK0

Input
To reduce the amount of noise in the power supply connected to the MC68020/EC020 and to provide for the instantaneous current requirements, common capacitive decoupling techniques should be observed. While there is no recommended layout for this capacitive decoupling, it is essential that the inductance and distance between these devices and the MC68020/EC020 be minimized to provide sufficiently fast response time to satisfy momentary current demands and to maintain a constant supply voltage. It is suggested that high-frequency, high-quality capacitors be placed as close to the MC68020/EC020 as possible. Table 9-2 lists the VCC and GND pin assignments for the MC68EC020 PPGA RP suffix package. Table 9-3 lists the VCC and GND pin assignments for the MC68EC020 PQFP FG suffix package. Refer to Section 11 Ordering Information and Mechanical Data for the VCC and GND pin assignments for the MC68020 packages. When assigning capacitors to the VCC and GND pins, the noisier pins address and data buses should be heavily decoupled from the internal logic pins. Typical decoupling practices include a high-frequency, high-quality capacitor to decouple every device on the printed circuit board however, due to the power requirements and drive capability of the MC68020/EC020, each VCC pin should be decoupled with an individual capacitor. Motorola recommends using a capacitor in the range of µF to µF on each VCC pin on each device to provide filtering for most frequencies prevalent in a digital system. In addition to the individual decoupling, several bulk decoupling capacitors should be placed onto the printed circuit board with typical values in the range of 33 µF to 330 µF. When power and ground planes are used with an adequate number of high-frequency, highquality capacitors, the system noise will be reduced to the required levels, and the MC68020/EC020 will function properly. Similar decoupling techniques should also be observed for other VLSI devices in the system.

In addition to the capacitive decoupling of the power supply, care must be taken to ensure a low-impedance connection between all MC68020/EC020 VCC and GND pins and the system power supply. A solid power supply connection from the power and ground planes to the MC68020/EC020 VCC and GND pins, respectively, will meet this requirement. Failure to provide connections of sufficient quality between the MC68020/EC020 power pins and the system power supplies will result in increased assertion delays for external signals, decreased voltage noise margins, increased system noise, and possible errors in MC68020/EC020 internal logic.

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M68020 USER’S MANUAL

Table VCC and GND Pin MC68EC020 PPGA RP Suffix

Pin Group Address Bus Data Bus Internal Logic Clock

VCC B7, C7 K12, M9, N9 D1, D2, E12, E13

GND A1, A7, C8, D13 J13, L8, M1, M8 F11, F12, J1, J2

Table VCC and GND Pin MC68EC020 PQFP FG Suffix

Pin Group Address Bus Data Bus Internal Logic Clock

VCC 90 44, 57 7, 8, 70, 71

GND 72, 89, 100 26, 43, 58, 59 3, 20, 21, 68, 69

CLOCK DRIVER

The MC68020/EC020 is designed to sustain high performance while using low-cost memory subsystems. The MC68020/EC020 requires a stable clock source that is free of ringing and ground bounce, has sufficient rise and fall times, and meets the minimum and maximum high and low cycle times. The individual system may require additional clocks for peripherals with a minimum amount of clock skew. Two possible clock solutions are provided with the MC88916 and MC74F803. Many other clock solutions can be used. Some crystal clock drivers are capable of driving the MC68020/EC020 directly. For slower speed designs, a simple 74F74 flip-flop meets the clocking needs of the MC68020/EC020. Coupled with the MC88916 or MC74F803 clock generation and distribution circuit, the MC68020/EC020 provides simple interface to lower speed memory subsystems. The MC88916 see Figure 9-7 and MC74F803 see Figure 9-8 generate the clock signals required to minimize the skew between different clocks to multiple devices such as coprocessors, synchronous state machines, DRAM controllers, and memory subsystems. The MC88916 clock driver can be used in doubling and synchronizing a low-frequency clock source. The MC74F803 will provide a controlled skew output for clocking other peripherals.
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12.5-MHz OSCILLATOR

CONTROLLER CLOCK 25 MHz

MC88916

CLOCK 2 50 MHz

BUS CLOCKS 25 MHz

CLOCK 25 MHz

MC68020/EC020 25 MHz

Figure High-Resolution Clock Controller
50-MHz OSCILLATOR

MC74F803

CONTROLLER CLOCK 25 MHz

MC68020/EC020 25 MHz

CLOCK
25 MHz

BUS CLOCKS 25 MHz

Figure Alternate Clock Solution

MEMORY INTERFACE

The MC68020/EC020 is capable of running an external bus cycle in a minimum of three clocks refer to Section 5 Bus Operation . The MC68020/EC020 runs an asynchronous bus cycle, terminated by the DSACK1/DSACK0 signals, and has a minimum duration of three controller clock periods in which up to four bytes 32 bits are transferred.

During read operations, the MC68020/EC020 latches data on the last falling clock edge of the bus cycle, one-half clock before the bus cycle ends. Latching data here, instead of the next rising clock edge, helps to avoid data bus contention with the next bus cycle and allows the MC68020/EC020 to receive the data into its execution unit sooner for a net performance increase.

Write operations also use this data bus timing to allow data hold times from the negating strobes and to avoid any bus contention with the following bus cycle. This MC68020/EC020 characteristic allows the system to be designed with a minimum of bus buffers and latches.

One benefit of the MC68020/EC020 on-chip instruction cache is that the effect of external wait states on performance is lessened because the caches are always accessed in fewer than “no wait states,” regardless of the external memory configuration.

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9-11
SECTION 11 ORDERING INFORMATION AND MECHANICAL DATA
This section contains the pin assignments and package dimensions of the MC68020 and the MC68EC020. In addition, detailed information is provided to be used as a guide when ordering.
STANDARD ORDERING INFORMATION
Standard MC68020 Ordering Information

Package Type Ceramic Pin Grid Array

RC Suffix

Plastic Quad Flat Pack FC Suffix

Plastic Pin Grid Array RP Suffix

Ceramic Quad Flat Pack FE Suffix

Frequency MHz Temperature °C
0 to 70 0 to 70 0 to 70 0 to 70
0 to 70 0 to 70 0 to 70
0 to 70 0 to 70 0 to 70
0 to 70 0 to 70 0 to 70 0 to 70

Order Number

MC68020RC16 MC68020RC20 MC68020RC25 MC68020RC33

MC68020FC16 MC68020FC20 MC68020FC25

MC68020RP16 MC68020RP20 MC68020RP25

MC68020FE16 MC68020FE20 MC68020FE25 MC68020FE33
Standard MC68EC020 Ordering Information

Package Type Plastic Pin Grid Array

RP Suffix

Plastic Quad Flat Pack FG Suffix

Frequency MHz Temperature °C
0 to 70 0 to 70
0 to 70 0 to 70

Order Number

MC68EC020RP16 MC68EC020RP25

MC68EC020FG16 MC68EC020FG25

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PIN ASSIGNMENTS AND PACKAGE DIMENSIONS MC68020 RC and RP Assignment

N D31 D28 D25 D22 D20 D17 GND VCC D14 D12 D9 D8 VCC

M DS D29 D26 D24 D21 D18 D16 VCC D13 D10 D6 D5 D4

L AS R/W D30 D27 D23 D19 GND D15 D11 D7 GND D3 D2

GND HALT GND

D1 D0

DSACK1 BERR GND

IPL0 IPL1

CDIS AVEC DSACK0

IPL2 GND

G ECS SIZ1 DBEN

MC68020

VCC GND VCC

SIZ0 FC2 FC1

GND IPEND

E FC0 RMC VCC

A2 OCS

VCC C

A4 A3

RESET CLK GND A0 A29 A25 A21 A17 A16 A12 A9 A7 A5

B GND BG BR A30 A27 A24 A20 A18 GND A15 A13 A10 A6

A BGACK A1 A31 A28 A26 A23 A22 A19 VCC GND A14 A11 A8
1 2 3 4 5 6 7 8 9 10 11 12 13

The VCC and GND pins are separated into four groups to provide individual power supply connections for the address bus buffers, data bus buffers, and all other output buffers and internal logic. It is recommended that all pins be connected to power and ground as indicated.

Group Address Bus

Data Bus Logic Clock

VCC A9, D3 M8, N8, N13 D1, D2, E3, G11, G13

GND A10, B9, C3, F12 L7, L11, N7, K3 G12, H13, J3, K1
OCS Signal, 3-4, 5-3 Ordering Information

MC68020, 11-1 MC68EC020, 11-1 Overlap, 8-3

Package Dimensions

MC68020 FC Suffix, 11-6 MC68020 FE Suffix, 11-7 MC68020 RC Suffix, 11-3 MC68020 RP Suffix, 11-4 MC68EC020 FG Suffix, 11-11 MC68EC020 RP Suffix, 11-9 Pin Assignment MC68020 FC Suffix, 11-5 MC68020 FE Suffix, 11-5 MC68020 RC Suffix, 11-2 MC68020 RP Suffix, 11-2 MC68EC020 FG Suffix, 11-10 MC68EC020 RP Suffix, 11-8 Port Size, 5-1, 5-5, 5-21, 9-5 Power Supply, 3-7, 9-9 Primitive, 7-4, 7-27 Busy Response Primitive, 7-30 CA Bit, 7-29 DR Bit, 7-29 Evaluate and Transfer Effective Address

Primitive, 7-35 Evaluate Effective Address and Transfer Data

Primitive, 7-35 Format, 7-28 Null Coprocessor Response Primitive, 7-31 PC Bit, 7-29 Supervisor Check Primitive, 7-33 Take Address and Transfer Data Primitive,
7-39 Take Midinstruction Exception Primitive, 7-47 Take Postinstruction Exception Primitive,
7-48 Take Preinstruction Exception Primitive, 7-45 Transfer from Instruction Stream Primitive,
7-34 Transfer Main Processor Control Register

Primitive, 7-41 Transfer Multiple Coprocessor Registers

Primitive, 7-42 Transfer Multiple Main Processor Registers

Primitive, 7-42 Transfer Operation Word Primitive, 7-33 Transfer Single Main Processor Register

Primitive, 7-40

INDEX-4

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Transfer Status Register and the scanPC Primitive, 7-44

Transfer to/from Top of Stack Primitive, 7-40 Write to Previously Evaluated Effective

Address Primitive, 7-37 Privilege Level, 2-2

Changing, 2-3 Supervisor Level, 1-4, 2-2 User Level, 1-4, 2-2 Privilege Violation Exception, 6-7, 6-8 Processing States, 2-1 Program Counter PC , 1-4 Programming Model, 1-4, 7-1, 7-2

Read Cycle, 5-3, 5-4, 5-8, 5-14, 5-16, 5-18, 5-22,
5-26 Byte Read Cycle, 5-26 Long-Word Read Cycle, 5-26, 8-2 Timing, 5-26

Read-Modify-Write Cycle, 5-3, 5-39, 5-42 Timing, 5-39

Registers Address Registers, 1-4 CAAR, 1-7, 4-3, 4-4 CACR, 1-7, 4-2, 4-3 Data Registers, 1-4 DFC, 1-7 Internal Cache Holding Register, 5-21 Program Counter PC , 1-4 SFC, 1-7 SR, 1-7, 4-1 VBR, 1-7

Reset, 4-3 Flowchart, 6-4 Reset Exception, 6-4 RESET Instruction, 7-58 RESET Signal, 3-6, 5-76, 6-4

Reset Exception, 6-4 RESET Instruction, 5-76 RESET Signal, 3-6, 5-76, 6-4 Retry, 5-56 RMC Signal, 3-4, 5-3, 5-39 RTE Instruction, 6-19, 6-24 RTM Instruction, 9-14, 9-16, 9-19 R/W Signal, 3-4, 5-2, 5-3, 9-5

S-bit SR , 1-7, 2-2, 2-3 Save and Restore Operations, 8-40 scanPC, 7-28 Sequencer, 8-2, 8-5 Shift/Rotate Instructions, 8-34 Signal s , 3-8

A1,A0, 5-2, 5-7, 5-9, 5-21, 9-5 7-6 7-6 4-1, 5-3 Address Bus, 3-2, 5-3 AS, 3-4, 5-2, 5-3 AVEC, 3-5, 5-4, 5-48, 5-53 BERR, 3-7, 5-4, 5-25, 5-53, 5-55, 6-4 BG, 3-6, 5-63, 5-66, 5-70, 5-71 BGACK, 3-6, 5-62, 5-63, 5-66 BR, 3-6, 5-63, 5-66, 5-70 Byte Select Control Signals, 9-5 CDIS, 3-7, 4-3 CLK, 3-7 3-2, 5-3 DBEN, 3-5, 5-4 DS, 3-4, 5-4, 5-21 DSACK1, DSACK0, 3-5, 5-4, 5-5, 5-24, 5-46,
5-53, 9-5 ECS, 3-4, 5-3 2-4, 3-2, 5-2, 5-3, 5-44, 7-6 Functional Groups, 3-1 HALT, 3-7, 5-4, 5-25, 5-53, 5-60 Input Signal, 5-2 Internal Signal, 5-2 IPEND, 3-5, 6-14 3-5, 6-11 OCS, 3-4, 5-3 RESET, 3-6, 5-76, 6-4 RMC, 3-4, 5-3, 5-39 R/W, 3-4, 5-2, 5-3, 9-5 SIZ1, SIZ0, 3-2, 5-2, 5-3, 5-7, 5-9, 5-21, 9-5 Single-Operand Instruction, 8-33 SIZ1, SIZ0 Signals, 3-2, 5-2, 5-3, 5-7, 5-9, 5-21, 9-5 Source Function Code Register SFC , 1-7 Special-Purpose MOVE Instruction, 8-29 Special Status Word SSW , 6-21 Spurious Interrupt, 5-48

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M68020 USER’S MANUAL

INDEX- 5

Stack Frame Midinstruction, 7-47 Postinstruction, 7-48 Preinstruction, 7-46

Status Register SR , 1-7, 4-1, 5-45, 6-1 STOP Instruction, 6-10 Supervisor Privilege Level, 1-4, 2-2 Supervisor Stack Pointer SSP , 1-4, 2-2 Synchronous Cycles, 5-24

T1, T0 Bits SR , 1-7, 6-9 TAS Instruction, 5-39 Thermal Characteristics, 10-1

MC68020, 10-2 MC68020 CQFP Package, 10-2 MC68EC020, 10-4 MC68EC020 PQFP Package, 10-4 Thermal Resistance, 10-2, 10-4 Timing, 5-26, 5-33 Trace Exception, 6-9 Trace Modes, 1-7 Tracing, 6-9

Transfer, 5-10, 5-14, 5-25 Bus Transfer, 5-1 Direction, 5-3 Misaligned, 5-1, 5-5 Operand Transfer, 5-1, 5-5

Trap Exception, 6-6

Unimplemented Instruction F-Line Opcode Exception, 6-7

User Privilege Level, 1-4, 2-2 User Stack Pointer USP , 1-4, 2-2

VCC Connections, 3-7, 9-9 Vector Base Register VBR , 1-7, 2-5, 6-2 Virtual Machine, 1-12 Virtual Memory, 1-10

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MC68EC020FG25 Datasheet file may be downloaded here without warranties.

Datasheet ID: MC68EC020FG25 635486