MC100ES8111FA

MC100ES8111FA Datasheet

The MC100ES8111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES8111 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems.

Part	Datasheet
MC100ES8111FA	MC100ES8111FA (pdf)

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Freescale Semiconductor Technical Data Low Voltage 1:10 Differential HSTL Clock Fanout Buffer The MC100ES8111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES8111 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems. • 1:10 differential clock fanout buffer • 80 ps maximum device skew • SiGe technology • Supports DC to 625 MHz operation of clock or data signals • HSTL compatible differential clock outputs • PECL and HSTL compatible differential clock inputs • V power supply for device core, V or V HSTL output supply • Supports industrial temperature range • Standard 32 lead LQFP package Functional Description The MC100ES8111 is designed for low skew clock distribution systems and supports clock frequencies up to 625 MHz. The device accepts two clock sources. The CLK0 input accepts HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 10 identical, differential HSTL compatible outputs. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all 10 outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The HSTL compatible output levels are generated with an open emitter architecture. This minimizes part-to-part and output-to-output skew. The open-emitter outputs require a 50 DC termination to GND 0 V . The output supply voltage can be either V or V, the core voltage supply is V. The output enable control is synchronized internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state true outputs logic low, inverted outputs logic high . The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The device is packaged in a 7x7 mm2 32-lead LQFP package. MC100ES8111 LOW-VOLTAGE 1:10 DIFFERENTIAL HSTL CLOCK FANOUT BUFFER FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 Freescale Semiconductor, Inc., All rights reserved. Freescale Confidential Proprietary, NDA Required / Preliminary VCC CLK0 VCC CLK1 CLK_SEL 24 23 22 21 20 19 18 17 VCCO VCC0 MC100ES8111 VCCO VCCO 12345678 CLK1 CLK1 CLK0 CLK0 CLK_SEL Figure MC100ES8111 Logic Diagram Figure 23-Lead Package Pinout Top View Table Pin Configuration 1 Pin CLK0, CLK0 CLK1, CLK1 I/O Input Type HSTL PECL Function Differential HSTL reference clock signal input Differential PECL reference clock signal input CLK_SEL OE Q[0-9], Q[0-9] Input Output LVCMOS

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Freescale Semiconductor Technical Data

Low Voltage 1:10 Differential HSTL Clock Fanout Buffer

The MC100ES8111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES8111 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver are high performance clock distribution in computing, networking and telecommunication systems.
• 1:10 differential clock fanout buffer
• 80 ps maximum device skew
• SiGe technology
• Supports DC to 625 MHz operation of clock or data signals
• HSTL compatible differential clock outputs
• PECL and HSTL compatible differential clock inputs
• V power supply for device core, V or V HSTL output supply
• Supports industrial temperature range
• Standard 32 lead LQFP package

Functional Description

The MC100ES8111 is designed for low skew clock distribution systems and supports clock frequencies up to 625 MHz. The device accepts two clock sources. The CLK0 input accepts HSTL compatible signals and CLK1 accepts PECL compatible signals. The selected input signal is distributed to 10 identical, differential HSTL compatible outputs.

In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all 10 outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated.

The HSTL compatible output levels are generated with an open emitter architecture. This minimizes part-to-part and output-to-output skew. The open-emitter outputs require a 50 DC termination to GND 0 V . The output supply voltage can be either V or V, the core voltage supply is V. The output enable control is synchronized internally preventing output runt pulse generation. Outputs are only disabled or enabled when the outputs are already in logic low state true outputs logic low, inverted outputs logic high . The internal synchronizer eliminates the setup and hold time requirements for the external clock enable signal. The device is packaged in a 7x7 mm2 32-lead LQFP package.

MC100ES8111

LOW-VOLTAGE 1:10 DIFFERENTIAL HSTL CLOCK

FANOUT BUFFER

FA SUFFIX 32-LEAD LQFP PACKAGE

CASE 873A-03

Freescale Semiconductor, Inc., All rights reserved. Freescale Confidential Proprietary, NDA Required / Preliminary

VCC CLK0

VCC CLK1

CLK_SEL
24 23 22 21 20 19 18 17

VCCO

VCC0

MC100ES8111

VCCO

VCCO
12345678

CLK1

CLK1

CLK0

CLK0

CLK_SEL

Figure MC100ES8111 Logic Diagram

Figure 23-Lead Package Pinout Top View

Table Pin Configuration 1

Pin CLK0, CLK0 CLK1, CLK1

I/O Input

Type HSTL PECL

Function Differential HSTL reference clock signal input Differential PECL reference clock signal input

CLK_SEL OE

Q[0-9], Q[0-9]

Input

Output

LVCMOS

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Datasheet ID: MC100ES8111FA 635470