ZL30407QCG1

ZL30407QCG1 Datasheet

ZL30407 SONET/SDH Network Element PLL

Part	Datasheet
ZL30407QCG1	ZL30407QCG1 (pdf)

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ZL30407 SONET/SDH Network Element PLL Data Sheet • Meets requirements of GR-253 for SONET Stratum 3 and SONET Minimum Clocks SMC • Meets requirements of GR-1244 for Stratum 3 • Meets requirements of G.813 Option 1 and 2 for SDH Equipment Clocks SEC • Generates clocks for ST-BUS, DS1, DS2, DS3, OC-3, E1, E3, STM-1 and MHz • Holdover accuracy of 4x10 -12 meets GR-1244 Stratum 3E and ITU-T G.812 requirements • Continuously monitors both references for frequency accuracy exceeding ±12 ppm • Provides “hit-less” reference switching • Compensates for Master Clock Oscillator accuracy • Automatically detects frequency of both reference clocks and synchronizes to any combination of 8 kHz, MHz, MHz and MHz reference frequencies • Allows Hardware or Microprocessor control • Pin compatible with ZL30410, ZL30402 and MT90401 November 2006 Ordering Information ZL30407QCC 80 Pin LQFP Trays ZL30407QCG1 80 Pin LQFP* Trays, Bake & Drypack *Pb Free Matte Tin -40°C to +85°C • Synchronization for SDH and SONET Network Elements • Clock generation for ST-BUS and GCI backplanes The ZL30407 is a Network Element Phase-Locked Loop designed to synchronize SDH and SONET systems. In addition, it generates multiple clocks for legacy PDH equipment and provides timing for STBUS and GCI backplanes. VDD GND C20i PRI PRIOR SEC SECOR RefSel HW RESET Primary Acquisition Secondary Acquisition Master Clock Frequency Calibration Microport Core PLL APLL Clock Synthesizer Control State Machine JTAG IEEE 1149.1a CS DS R/W A0-A6 D0-D7 MS1 MS2 RefAlign LOCK HOLDOVER C155P/N C34/C44 C19o C16o C8o C6o C4o C2o C1.5o F16o F8o F0o E3DS3/OC3 E3/DS3 Tclk Tdi Tdo Tms Trst R1-17 Figure 1 - Functional Block Diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. ZL30407 Data Sheet The ZL30407 operates in NORMAL LOCKED , HOLDOVER and FREE-RUN modes to ensure that in the presence of jitter, wander and interruptions to the reference signals, the generated clocks meet international standards. The filtering characteristics of the PLL are hardware or software selectable and they do not require any external adjustable components. The ZL30407 uses an external 20 MHz Master Clock Oscillator to provide a stable timing source for the HOLDOVER operation. The ZL30407 operates from a single V power supply and offers a 5 V tolerant microprocessor interface. Zarlink Semiconductor Inc. ZL30407 Data Sheet Table of Contents Change Summary 6 ZL30407 Pinout 6 Pin Connections 6 Functional Description 12 Acquisition PLLs 12 Core PLL 12 Digitally Controlled Oscillator DCO 13 Filters 13 Phase Slope Limiters 14 Lock Indicator LOCK 14 Reference Alignment RefAlign . 14 Using RefAlign with MHz, MHz or MHz Reference 14 Using RefAlign with an 8 kHz Reference 15 Clock Synthesizer 16 Output Clocks. 16 Output Clocks Phase Adjustment 17 Control State Machine 17 Clock Modes 17 ZL30407 State Machine 17 Reset State. 18 Free-Run State Free-Run mode 18 Normal State Normal Mode or Locked Mode . 18 Holdover State Holdover Mode 19 Auto Holdover State 19 State Transitions 20 Master Clock Frequency Calibration Circuit 20 Microprocessor Interface 21 JTAG Interface 21 Hardware and Software Control 21 Hardware Control 22 Control Pins 22 Status Pins 23 Software Control 23 Control Bits. 23 ZL30407 Register Map. 24 Change Updated Ordering Information ZL30407 Pinout Pin Connections IC DS NC LOCK NC HOLDOVER VDD C34/C44 GND C20i NC VDD RefAlign RefSel C19o GND IC C6o C1.5o PRIOR SECOR OE CS RESET HW D0 D1 D2 D3 GND IC VDD D4 D5 D6 D7 R/W A0 IC 60 58 56 54 52 50 48 46 44 42 40 62 38 64 36 66 34 68 32 ZL30407 72 28 74 26 76 24 78 22 80 2 4 6 8 10 12 14 16 18 20 NC Tdi Trst Tclk Tms Tdo NC GND C155P C155N VDD AVDD GND IC GND PRI SEC E3/DS3 E3DS3/OC3 IC A1 A2 A3 A4 GND A5 A6 FCS VDD GND F16o C16o C8o C4o C2o F0o MS1 MS2 F8o Figure 2 - Pin Connections for 80-pin LQFP package Zarlink Semiconductor Inc. Pin Description Pin # 1 2-5 Name IC A1-A4 A5-A6 F16o C16o ZL30407 Data Sheet Internal Connection. Leave unconnected. Address 1 to 4 5 V tolerant input . Address inputs for the parallel processor interface. Connect to ground in Hardware Control. Ground. Negative power supply. Address 5 to 6 5 V tolerant input . Address inputs for the parallel processor interface. Connect to ground in Hardware Control. Filter Characteristic Select Input . In Hardware Control, FCS selects the filtering characteristics of the ZL30407. Set this pin high to have a loop filter corner frequency of Hz and limit the phase slope to 885 ns/sec. Set this pin low to have corner frequency of Hz and limit the phase slope to 41 ns per ms. Connect to ground in Software Control. This pin is internally pulled down to GND. Positive Power Supply Ground Frame Pulse ST-BUS Mbps CMOS tristate output . This is an 8 kHz, 61 ns wide, active low framing pulse, which marks beginning of a ST-BUS frame. This frame pulse is typically used for ST-BUS operation at Mbps. Clock MHz CMOS tristate output . This clock is used for ST-BUS operation at Mbps. Clock MHz CMOS tristate output . This clock is used for ST-BUS operation at Mbps.

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ZL30407 SONET/SDH Network Element PLL

Data Sheet
• Meets requirements of GR-253 for SONET Stratum 3 and SONET Minimum Clocks SMC
• Meets requirements of GR-1244 for Stratum 3
• Meets requirements of G.813 Option 1 and 2 for SDH Equipment Clocks SEC
• Generates clocks for ST-BUS, DS1, DS2, DS3, OC-3, E1, E3, STM-1 and MHz
• Holdover accuracy of 4x10 -12 meets GR-1244 Stratum 3E and ITU-T G.812 requirements
• Continuously monitors both references for frequency accuracy exceeding ±12 ppm
• Provides “hit-less” reference switching
• Compensates for Master Clock Oscillator accuracy
• Automatically detects frequency of both reference clocks and synchronizes to any combination of 8 kHz, MHz, MHz and MHz reference frequencies
• Allows Hardware or Microprocessor control
• Pin compatible with ZL30410, ZL30402 and MT90401

November 2006
Ordering Information ZL30407QCC 80 Pin LQFP Trays ZL30407QCG1 80 Pin LQFP* Trays, Bake & Drypack
*Pb Free Matte Tin -40°C to +85°C
• Synchronization for SDH and SONET Network Elements
• Clock generation for ST-BUS and GCI backplanes

The ZL30407 is a Network Element Phase-Locked Loop designed to synchronize SDH and SONET systems. In addition, it generates multiple clocks for legacy PDH equipment and provides timing for STBUS and GCI backplanes.

VDD GND

C20i

PRI PRIOR

SEC SECOR

RefSel HW

RESET

Primary Acquisition

Secondary Acquisition

Master Clock Frequency Calibration

Microport

Core PLL

APLL

Clock Synthesizer

Control State Machine

JTAG IEEE 1149.1a

CS DS R/W A0-A6 D0-D7

MS1 MS2 RefAlign LOCK HOLDOVER

C155P/N C34/C44 C19o C16o C8o C6o C4o C2o C1.5o F16o F8o F0o

E3DS3/OC3 E3/DS3

Tclk Tdi Tdo Tms Trst

R1-17

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.

ZL30407

Data Sheet

The ZL30407 operates in NORMAL LOCKED , HOLDOVER and FREE-RUN modes to ensure that in the presence of jitter, wander and interruptions to the reference signals, the generated clocks meet international standards. The filtering characteristics of the PLL are hardware or software selectable and they do not require any external adjustable components. The ZL30407 uses an external 20 MHz Master Clock Oscillator to provide a stable timing source for the HOLDOVER operation.

The ZL30407 operates from a single V power supply and offers a 5 V tolerant microprocessor interface.

Zarlink Semiconductor Inc.

ZL30407

Data Sheet

Table of Contents

Change Summary 6

ZL30407 Pinout 6 Pin Connections 6

Functional Description 12 Acquisition PLLs 12 Core PLL 12 Digitally Controlled Oscillator DCO 13 Filters 13 Phase Slope Limiters 14 Lock Indicator LOCK 14 Reference Alignment RefAlign . 14 Using RefAlign with MHz, MHz or MHz Reference 14 Using RefAlign with an 8 kHz Reference 15 Clock Synthesizer 16 Output Clocks. 16 Output Clocks Phase Adjustment 17 Control State Machine 17 Clock Modes 17 ZL30407 State Machine 17 Reset State. 18 Free-Run State Free-Run mode 18 Normal State Normal Mode or Locked Mode . 18 Holdover State Holdover Mode 19 Auto Holdover State 19 State Transitions 20 Master Clock Frequency Calibration Circuit 20 Microprocessor Interface 21 JTAG Interface 21

Hardware and Software Control 21 Hardware Control 22 Control Pins 22 Status Pins 23 Software Control 23 Control Bits. 23 ZL30407 Register Map. 24
Change Updated Ordering Information

ZL30407 Pinout

Pin Connections

IC DS NC LOCK NC HOLDOVER VDD C34/C44 GND C20i NC VDD RefAlign RefSel C19o GND IC C6o C1.5o PRIOR

SECOR OE CS

RESET HW D0 D1 D2 D3

GND IC

VDD D4 D5 D6 D7 R/W A0 IC
60 58 56 54 52 50 48 46 44 42 40
62 38
64 36
66 34
68 32

ZL30407
72 28
74 26
76 24
78 22
80 2 4 6 8 10 12 14 16 18 20

NC Tdi Trst Tclk Tms Tdo NC GND C155P C155N VDD AVDD GND IC GND PRI SEC E3/DS3 E3DS3/OC3

IC A1 A2 A3 A4 GND A5 A6 FCS VDD GND F16o C16o C8o C4o C2o F0o MS1 MS2 F8o

Figure 2 - Pin Connections for 80-pin LQFP package

Zarlink Semiconductor Inc.

Pin Description Pin # 1 2-5

Name IC

A1-A4

A5-A6

F16o

C16o

ZL30407

Data Sheet

Internal Connection. Leave unconnected.

Address 1 to 4 5 V tolerant input . Address inputs for the parallel processor interface. Connect to ground in Hardware Control.

Ground. Negative power supply.

Address 5 to 6 5 V tolerant input . Address inputs for the parallel processor interface. Connect to ground in Hardware Control.

Filter Characteristic Select Input . In Hardware Control, FCS selects the filtering characteristics of the ZL30407. Set this pin high to have a loop filter corner frequency of Hz and limit the phase slope to 885 ns/sec. Set this pin low to have corner frequency of Hz and limit the phase slope to 41 ns per ms. Connect to ground in Software Control. This pin is internally pulled down to GND.

Positive Power Supply

Ground

Frame Pulse ST-BUS Mbps CMOS tristate output . This is an 8 kHz, 61 ns wide, active low framing pulse, which marks beginning of a ST-BUS frame. This frame pulse is typically used for ST-BUS operation at Mbps.

Clock MHz CMOS tristate output . This clock is used for ST-BUS operation at Mbps.

Clock MHz CMOS tristate output . This clock is used for ST-BUS operation at Mbps.

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Datasheet ID: ZL30407QCG1 649221