ZL30302GAG2

ZL30302GAG2 Datasheet

ZL30302 Timing over Packet ToP Technology

Part	Datasheet
ZL30302GAG2	ZL30302GAG2 (pdf)

Related Parts	Information
ZL30302GAG	ZL30302GAG

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ZL30302 Timing over Packet ToP Technology Data Sheet • Recovers and transmits network synchronization over Ethernet, IP and MPLS Networks • Output clocks meet ITU-T G.823 and G.824 traffic interface specifications, and ANSI T1.403 timing requirements • Fully configurable, enabling performance to be tailored to application and network requirements • Generates outgoing packet reference locked to the TS_CLKi electrical reference clock • Recovers up to 4 independent clock frequencies from packet streams, in the frequency range MHz to 10 MHz • Average frequency accuracy better than ± 15 ppb • Supports Master, Slave and Repeater modes of operation • Supports user defined timing recovery algorithms • Dual configurable packet interface • Two MII interfaces • One MII and one GMII/TBI • Flexible 32 bit host CPU interface Motorola PowerQUICCTM 1 and 2 compatible September 2005 Ordering Information ZL30302GAG 324 PBGA -40°C to +85°C Trays • Flexible classification of incoming packets at layers 2, 3, 4 and 5 • Flexible, multi-protocol packet encapsulation, with support for Ethernet, VLAN, IPv4/6, MPLS, L2TPv3, UDP and RTP • JTAG IEEE 1149 boundary-scan interface • GSM, UMTS air interface synchronization over a packet network • Circuit Emulation Service over Packets CESoP , TDM over IP TDMoIP • IP-PBX • VoIP Gateways • Video Conferencing • Broadband Video Distribution Host Processor running Zarlink Timing Recovery Algorithm GMII/TBI or MII ZL30302 Host Processor Interface Packet Engine Timestamp Engine Clock Synthesis JTAG CLKo[0] CLKo[1] CLKo[2] CLKo[3] CLKi[0] CLKi[1] CLKi[2] CLKi[3] EXT_CLKo_REF TS_CLKi TCK TDI TDO TMS TRST Figure 1 - ZL30302 Functional Block Diagram Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved. ZL30302 Data Sheet Zarlink Semiconductor Inc. ZL30302 Data Sheet Table of Contents Description 6 Physical Specification 6 External Interface Description 11 Clock Interface. 11 Packet Interfaces. 12 CPU Interface 17 System Function Interface. 19 Test Facilities. 20 Administration, Control and Test Interface. 20 JTAG Interface 20 Miscellaneous Inputs 21 Power and Ground Connections 21 Internal Connections 22 Device ID 22 Typical Applications 23 Edge of the PSN 23 Wireless Access Applications 24 Functional Description 25 Modes of Operation 25 Master Mode of Operation 25 Slave Mode of Operation 27 Timing Repeater Mode of Operation 28 Timing Redundancy. 29 Clock Recovery 29 Adaptive Clock Recovery 29 Differential Clock Recovery 31 Combination of Adaptive and Differential Clock Recovery. 32 Handling of Non-Timing Packets 34 Snoop Mode. 34 Pass-through Mode 34 Standalone Mode 35 Contribution of the Network and Local Oscillator on the performance 35 CPU Interface 36 Management and Clock Quality Statistics 37 Statistics on Received Timing Packets Slave mode 37 Statistics on Transmitted Timing Packets Master Mode 38 Status Information on Recovered Clocks. 38 Processing of Incoming Packets 39 System Features 40 Loopback Modes 40 Host Packet Generation 40 Power Up Sequence 40 JTAG Interface and Board Level Test Features 41 External Component Requirements 41 Miscellaneous Features. 41 Test Modes Operation 41 Overview 41 System Normal Mode 42 System Tri-State Mode. 42 Test Mode Control 42 System Normal Mode. 42 Zarlink Semiconductor Inc. ZL30302 Data Sheet Table of Contents

PDF Datasheet Preview

ZL30302 Timing over Packet ToP Technology

Data Sheet
• Recovers and transmits network synchronization over Ethernet, IP and MPLS Networks
• Output clocks meet ITU-T G.823 and G.824 traffic interface specifications, and ANSI T1.403 timing requirements
• Fully configurable, enabling performance to be tailored to application and network requirements
• Generates outgoing packet reference locked to the TS_CLKi electrical reference clock
• Recovers up to 4 independent clock frequencies from packet streams, in the frequency range MHz to 10 MHz
• Average frequency accuracy better than ± 15 ppb
• Supports Master, Slave and Repeater modes of operation
• Supports user defined timing recovery algorithms
• Dual configurable packet interface
• Two MII interfaces
• One MII and one GMII/TBI
• Flexible 32 bit host CPU interface Motorola PowerQUICCTM 1 and 2 compatible

September 2005
Ordering Information ZL30302GAG 324 PBGA
-40°C to +85°C

Trays
• Flexible classification of incoming packets at layers 2, 3, 4 and 5
• Flexible, multi-protocol packet encapsulation, with support for Ethernet, VLAN, IPv4/6, MPLS, L2TPv3, UDP and RTP
• JTAG IEEE 1149 boundary-scan interface
• GSM, UMTS air interface synchronization over a packet network
• Circuit Emulation Service over Packets CESoP , TDM over IP TDMoIP
• IP-PBX
• VoIP Gateways
• Video Conferencing
• Broadband Video Distribution

Host Processor running Zarlink Timing Recovery Algorithm

GMII/TBI or MII

ZL30302

Host Processor Interface

Packet Engine

Timestamp Engine

Clock Synthesis

JTAG

CLKo[0] CLKo[1] CLKo[2] CLKo[3]

CLKi[0] CLKi[1] CLKi[2] CLKi[3]

EXT_CLKo_REF TS_CLKi

TCK TDI TDO TMS TRST

Figure 1 - ZL30302 Functional Block Diagram

Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.

ZL30302

Data Sheet

Zarlink Semiconductor Inc.

ZL30302

Data Sheet

Table of Contents

Description 6

Physical Specification 6

External Interface Description 11 Clock Interface. 11 Packet Interfaces. 12 CPU Interface 17 System Function Interface. 19 Test Facilities. 20 Administration, Control and Test Interface. 20 JTAG Interface 20 Miscellaneous Inputs 21 Power and Ground Connections 21 Internal Connections 22 Device ID 22

Typical Applications 23 Edge of the PSN 23 Wireless Access Applications 24

Functional Description 25 Modes of Operation 25 Master Mode of Operation 25 Slave Mode of Operation 27 Timing Repeater Mode of Operation 28 Timing Redundancy. 29 Clock Recovery 29 Adaptive Clock Recovery 29 Differential Clock Recovery 31 Combination of Adaptive and Differential Clock Recovery. 32 Handling of Non-Timing Packets 34 Snoop Mode. 34 Pass-through Mode 34 Standalone Mode 35 Contribution of the Network and Local Oscillator on the performance 35 CPU Interface 36 Management and Clock Quality Statistics 37 Statistics on Received Timing Packets Slave mode 37 Statistics on Transmitted Timing Packets Master Mode 38 Status Information on Recovered Clocks. 38 Processing of Incoming Packets 39

System Features 40 Loopback Modes 40 Host Packet Generation 40 Power Up Sequence 40 JTAG Interface and Board Level Test Features 41 External Component Requirements 41 Miscellaneous Features. 41 Test Modes Operation 41 Overview 41 System Normal Mode 42 System Tri-State Mode. 42 Test Mode Control 42 System Normal Mode. 42

Zarlink Semiconductor Inc.

ZL30302

Data Sheet

Table of Contents

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Datasheet ID: ZL30302GAG2 649220